2008 International Symposium on System-on-Chip最新文献

Micronmesh for fault-tolerant GALS Multiprocessors on FPGA FPGA上容错GALS多处理器微网格

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694870

H. Kariniemi, J. Nurmi

{"title":"Micronmesh for fault-tolerant GALS Multiprocessors on FPGA","authors":"H. Kariniemi, J. Nurmi","doi":"10.1109/ISSOC.2008.4694870","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694870","url":null,"abstract":"System-on-Chip (SoC) circuits have evolved to single chip Multiprocessor systems. Due to increasing variance of process parameters, which produces synchronization problems on large SoCs, a globally-asynchronous locally-synchronous (GALS) design style must have been mobilized. In addition, the large VLSI circuits are also becoming more susceptible to transient and intermittent faults which can corrupt their operation. This paper presents a new micronmesh network-on-chip (NoC) which is targeted to fault-tolerant communication of GALS Multiprocessor SoCs (MPSoC). It is fully synthesizable with current design tools and it can be used for prototyping MPSoCs on FPGA circuits. The Micronmesh incorporates a new improved fault-diagnosis-and-repair (FDAR) system which is able to diagnose and repair also buffer memories in addition to wire connections while fault-tolerant DOR (FTDOR) routing is used for routing packets to their destinations around defected parts. Owing to the FDAR system and the FTDOR Micronmesh degrades gracefully as permanent faults appear and it is able to recover from transient and intermittent faults. The fault-tolerance of the Micronmesh is also improved by switch-to-switch (S2S) level retransmissions which reduce the number of end-to-end (E2E) level retransmissions that produce considerably higher latencies. These methods targeted at improving the fault-tolerance are also becoming necessary for improving the manufacturability of the circuits in the future.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"779 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122626449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Trade-offs in mapping high-level dataflow graphs onto ASIPs 将高级数据流图映射到api的权衡

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694876

V. Guzma, S. Bhattacharyya, Pertti Kellomäki, J. Takala

引用次数: 2

Evaluation of heterogeneous multiprocessor architectures by energy and performance optimization 基于能量和性能优化的异构多处理器体系结构评估

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694884

Heikki Orsila, E. Salminen, Marko Hännikäinen, T. Hämäläinen

{"title":"Evaluation of heterogeneous multiprocessor architectures by energy and performance optimization","authors":"Heikki Orsila, E. Salminen, Marko Hännikäinen, T. Hämäläinen","doi":"10.1109/ISSOC.2008.4694884","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694884","url":null,"abstract":"Design space exploration aims to find an energy-efficient architecture with high performance. A trade-off is needed between these goals, and the optimization effort should also be minimized. In this paper, we evaluate heterogeneous multiprocessor architectures by optimizing both energy and performance for applications. Ten random task graphs are optimized for each architecture, and evaluated with simulations. The energy versus performance trade-off is analyzed by looking at Pareto optimal solutions. It is assumed that there is a variety of processing elements whose number, frequency and microarchitecture can be modified for exploration purposes. It is found that both energy-efficient and well performing solutions exist, and in general, performance is traded for energy-efficiency. Results indicate that automated exploration tools are needed when the complexity of the mapping problem grows, starting already with our experiment setup: 6 types of PEs to select from, and the system consists of 2 to 5 PEs. Our results indicate that our Simulated Annealing method can be used for energy optimization with heterogeneous architectures, in addition to performance optimization with homogeneous architectures.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128703723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

PER performance enhancement through antenna and transceiver co-design for multi-band OFDM UWB communication 多频带OFDM UWB通信中天线与收发器协同设计提高PER性能

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694875

Peng Wang, H. Tenhunen, Dian Zhou, Lirong Zheng

引用次数: 0

Energy analysis of re-injection based deadlock recovery routing algorithms 基于重注入的死锁恢复路由算法能量分析

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694864

H. Kooti, M. Mirza-Aghatabar, S. Hessabi, Arash Tavakkol

引用次数: 0

A state based framework for efficient system-level power estimation of of costum reconfigurable cores 基于状态的可重构内核系统级功率估计框架

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694889

A. Ahmadinia, Balal Ahmad, T. Arslan

引用次数: 2

Analyzing models of computation for software defined radio applications 软件无线电应用计算模型分析

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694886

H. Berg, C. Brunelli, Ulf Lücking

引用次数: 30

Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays 粗粒可重构阵列中高速乘法器的集成

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694885

Stavros Georgiopoulos, G. Dimitroulakos, C. Goutis

{"title":"Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays","authors":"Stavros Georgiopoulos, G. Dimitroulakos, C. Goutis","doi":"10.1109/ISSOC.2008.4694885","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694885","url":null,"abstract":"The efficiency of a Coarse Grained Reconfigurable Array architecture in terms of performance and hardware cost is hard to be determined. Until now, few case studies have been published to determine the impact of the architecture parameters on the Instructions per Cycle and the architecture area. However, none of those have considered the impact of multipliers embedded in the Processing Elements of Coarse Grain Reconfigurable Array architectures. This paper focuses on multipliers both from the compiler and the architecture perspective. An already existing exploration framework has been used for our study. It consists of two parts: a) an existing retargetable compiler from which the mapping efficiency is estimated and b) from the parametric realization of the coarse grained reconfigurable array in hardware description language (VHDL). The latter is used as input in the Synopsys Design Compiler for the estimation of the area and clock frequency of each architecture instance. The system has been realized using the 0.13 mum process of ASIC technology. The experiments report the system area, clock frequency and performance for different embedded multipliers.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Congestion-aware task mapping in heterogeneous MPSoCs 异构mpsoc中的拥塞感知任务映射

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694878

Ewerson Carvalho, F. Moraes

引用次数: 80

A 110 dB, 3-mW fourth-order Σ-Δ modulator for atmospheric pressure sensor 用于大气压力传感器的110 dB, 3 mw四阶Σ-Δ调制器

2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694888

Taeyoon Kim, Wonki Park, Hee-Sun Ahn, Kyongwon Min, Sangyong Lee, Jongchan Choi, Chulwoo Kim, Kynnyun Kim, Sungchul Lee

引用次数: 0