{"title":"Balancing wrapper chains of SoC core based on best interchange decreasing","authors":"Maoxiang Yi, Huaguo Liang, Zhengfeng Huang","doi":"10.1109/ISSOC.2008.4694880","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694880","url":null,"abstract":"An improved scheme for balancing wrapper chains partition of SoC core is proposed. Starting with the primary configuration created by LPT algorithm, we optimizes the current partition through the best interchange decreasing and iterative operation, in each step of which a pair of wrapper chains with maximum length difference is selected and the optimal two cells in the two wrapper chains are interchanged. Experiments are executed for the typical cores of the ITCpsila02 benchmarks. The results show that compared to the previous techniques, our scheme can create more balanced wrapper chains, decreasing the maximum scan shift length, hence the test application time of core.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123018574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Inherent reliability evaluation of Networks-on-Chip based on analytical models","authors":"M. Valinataj, S. Mohammadi, S. Safari","doi":"10.1109/ISSOC.2008.4694867","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694867","url":null,"abstract":"Reliability evaluation based on analytical models is a precise method for dependability analysis before and after designing the fault-tolerant systems. In this paper, we present the precise formulations for the inherent reliability of mesh-based NoCs that also depend on the employed routing algorithm and traffic model. Based on this analysis, the effects of some permanent failures in the links, switches or cores on the packet delivery of NoCs are determined. The models can be extended to evaluate the fault-tolerant methods in addition to other topologies and routing algorithms.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122909263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the credibility of load-latency measurement of network-on-chips","authors":"E. Salminen, A. Kulmala, T. Hämäläinen","doi":"10.1109/ISSOC.2008.4694860","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694860","url":null,"abstract":"This paper studies the impact of various simulation and network-on-chip (NoC) setups in common load-latency curves that are used for performance evaluation. The different setups yield very large variation in the observed performance yet they are too often undocumented. Vague definitions make the comparison of NoCs hard or impossible since the large uncertainties hide the actual differences between compared networks. Hence, this paper presents guidelines for performing load-latency measurements for network-on-chips to avoid these pitfalls.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125263900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An ASIC-design-based configurable SOC architecture for networked media","authors":"Ning Ma, Z. Pang, H. Tenhunen, Lirong Zheng","doi":"10.1109/ISSOC.2008.4694877","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694877","url":null,"abstract":"An ASIC-design-based configurable SOC architecture, which is high performance, flexible, programmable, and compiler-independent, is designed for networked media applications. A coarse-grained parallel computing mechanism is employed in this architecture. Mapping this architecture to a specific application is demonstrated through an example in multimedia application. The design is validated in a powerful FPGA, consisting of two CPUs, working at 81 MHz and five function units, working at 40.5 MHz.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122355730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A flexible modeling and simulation framework for Design Space Exploration","authors":"Camille Jalier, D. Lattard, G. Sassatelli","doi":"10.1109/ISSOC.2008.4694863","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694863","url":null,"abstract":"Applications like 4G baseband modem require single-chip implementation to meet the integration and the power consumption requirements. These applications involve a high computation performance with real-time constraints, low power consumption and low cost. The concept of MPSoC is well suited to this problem. It makes it possible to adjust the architecture, by allocating the computational power where it is needed to fit the application needs. This often implies that the software has to be developed at the same time the platform is refined. Algorithm designers need accurate performance estimation to guide their decisions and system architects need to provide a design with enough calculation capacity and flexibility. Based on the methodology used for the design of the 4G FAUST chipset, this paper presents a modeling and simulation framework for Design Space Exploration (DSE) which enables a rapid evaluation of the application-to-platform adequation. The key element of this work is a simple and flexible way of modeling application and architecture. Our SystemC-based simulation environment can support a broad range of architecture components (ASIC, DSP, NoC, bus, shared or distributed memory, ...) and application features (control flow, data exchange, interrupts, data-dependent processing, dynamic reconfiguration). Application and architecture models are separated to allow independent design space exploration. The simulation basically executes the algorithms on the architecture and monitors dynamic behavior such as communication transfers, resource conflicts, starvation, dynamic reconfiguration, etc.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132534965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of power-management granularity on the energy-quality trade-off for soft and hard real-time applications","authors":"Aleksandar Milutinovic, K. Goossens, G. Smit","doi":"10.1109/ISSOC.2008.4694891","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694891","url":null,"abstract":"In this paper we introduce the concepts of work of tokens (e.g. video frames) in an application, and slack arising from variations in work. Slack is used for dynamic voltage and frequency scaling in combination with a conservative power-management policy that never misses deadlines, for hard real-time applications, and with a non-conservative policy for soft real-time applications. We evaluate both policies for a number of different granularities (frequency of activation of the power manager) on an MPEG4 application, on energy and quality (deadline misses). We conclude that for soft real-time applications, there is a clear optimum in the energy, which depends on the work histogram of the application. The conservative policy has no deadline misses, and is only negligibly more expensive in terms of energy than the non-conservative policy. Finally, the granularity of both policies can be very coarse (128 frames) to reduce the power manager activation frequency, which has an insignificant energy cost.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"135 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131157404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}