{"title":"基于最佳交换递减的SoC核心包装链平衡","authors":"Maoxiang Yi, Huaguo Liang, Zhengfeng Huang","doi":"10.1109/ISSOC.2008.4694880","DOIUrl":null,"url":null,"abstract":"An improved scheme for balancing wrapper chains partition of SoC core is proposed. Starting with the primary configuration created by LPT algorithm, we optimizes the current partition through the best interchange decreasing and iterative operation, in each step of which a pair of wrapper chains with maximum length difference is selected and the optimal two cells in the two wrapper chains are interchanged. Experiments are executed for the typical cores of the ITCpsila02 benchmarks. The results show that compared to the previous techniques, our scheme can create more balanced wrapper chains, decreasing the maximum scan shift length, hence the test application time of core.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"200 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Balancing wrapper chains of SoC core based on best interchange decreasing\",\"authors\":\"Maoxiang Yi, Huaguo Liang, Zhengfeng Huang\",\"doi\":\"10.1109/ISSOC.2008.4694880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An improved scheme for balancing wrapper chains partition of SoC core is proposed. Starting with the primary configuration created by LPT algorithm, we optimizes the current partition through the best interchange decreasing and iterative operation, in each step of which a pair of wrapper chains with maximum length difference is selected and the optimal two cells in the two wrapper chains are interchanged. Experiments are executed for the typical cores of the ITCpsila02 benchmarks. The results show that compared to the previous techniques, our scheme can create more balanced wrapper chains, decreasing the maximum scan shift length, hence the test application time of core.\",\"PeriodicalId\":168022,\"journal\":{\"name\":\"2008 International Symposium on System-on-Chip\",\"volume\":\"200 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Symposium on System-on-Chip\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSOC.2008.4694880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Symposium on System-on-Chip","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSOC.2008.4694880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Balancing wrapper chains of SoC core based on best interchange decreasing
An improved scheme for balancing wrapper chains partition of SoC core is proposed. Starting with the primary configuration created by LPT algorithm, we optimizes the current partition through the best interchange decreasing and iterative operation, in each step of which a pair of wrapper chains with maximum length difference is selected and the optimal two cells in the two wrapper chains are interchanged. Experiments are executed for the typical cores of the ITCpsila02 benchmarks. The results show that compared to the previous techniques, our scheme can create more balanced wrapper chains, decreasing the maximum scan shift length, hence the test application time of core.