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Real-time execution monitoring on multi-processor system-on-chip 多处理器片上系统的实时执行监控
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694872
K. Holma, Tero Arpinen, E. Salminen, Marko Hännikäinen, T. Hämäläinen
{"title":"Real-time execution monitoring on multi-processor system-on-chip","authors":"K. Holma, Tero Arpinen, E. Salminen, Marko Hännikäinen, T. Hämäläinen","doi":"10.1109/ISSOC.2008.4694872","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694872","url":null,"abstract":"In system-level design, design space exploration (DSE) produces large amounts of data when exploring myriad of alternatives for application mapping and the underlying platform. Visualization of the essential execution data makes the right design decisions essentially easier. This paper presents execution monitor, a versatile monitoring tool implemented in Java, for multi-processor systems-on-chip (MPSoCs). It allows monitoring both the application and the underlying platform in real-time, and also viewing the previously recorded execution trace. Execution monitor can be used both during the simulation and prototyping. Moreover, the designer can rapidly evaluate in run-time the performance of multiple application mappings via intuitive drag-and-drop mechanism. The case study shows that the visualization of the monitored execution data significantly eases optimizing the performance of the video codec after addition of new application functionality.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133436257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-Objective Genetic optimized multiprocessor SoC design 多目标遗传优化的多处理器SoC设计
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694887
M. Arjomand, H. Sarbazi-Azad, S. Amiri
{"title":"Multi-Objective Genetic optimized multiprocessor SoC design","authors":"M. Arjomand, H. Sarbazi-Azad, S. Amiri","doi":"10.1109/ISSOC.2008.4694887","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694887","url":null,"abstract":"In this paper, we introduce a new multi-objective genetic algorithm (MOGA) for mapping a given set of intellectual property onto a network-on-chip architecture such that for a specific application total communication cost and energy consumption become optimized while bandwidth constraints are satisfied. As the main theoretical contribution, we first introduce a generic queuing model to estimate performance and an experimental energy consumption model during the design phase, with acceptable accuracy. Then, an efficient genetic algorithm employs these models to propose a Pareto optimal front for an application and an arbitrary topology. Experimental results show that the proposed algorithm is very fast which results in a new approach for mapping MPSoC cores on chip.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115684943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Synthesis for variable pipelined function units 可变流水线功能单元的综合
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694874
Y. Ben-Asher, Nadav Rotem
{"title":"Synthesis for variable pipelined function units","authors":"Y. Ben-Asher, Nadav Rotem","doi":"10.1109/ISSOC.2008.4694874","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694874","url":null,"abstract":"Usually, in high level hardware synthesis, all functional units of the same type have a fixed known ldquolengthrdquo (number of stages) and the scheduler mainly determines when each unit is activated. We focus on scheduling techniques for the high-level synthesis of pipelined functional units where the number of stages of these operations is a free parameter of the synthesis. This problem is motivated by the ability to create pipelined functional units, such as multipliers, with different pipe lengths. These units have different characteristics in terms of parallelism level, frequency, latency, etc. In this paper presents the variable pipeline scheduler (VPS). The ability to synthesize variable pipelined units expands the known scheduling problem of high-level synthesis to include a 2D search for a minimal number of instances and their desired number of stages. The proposed search procedure is based on algorithms that find a local minima in a d-dimensional grid, thus avoiding the need to evaluate all possible points in the space. We have implemented a C language compiler for VPS. Our results demonstrate that using variable pipeline units can reduce the overall resource usage and improve the execution time.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114775867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Area-efficient low-cost low-dropout regulators using MOS capacitors 使用MOS电容器的面积高效低成本低差稳压器
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694856
H. Aminzadeh, R. Lotfi, K. Mafinezhad
{"title":"Area-efficient low-cost low-dropout regulators using MOS capacitors","authors":"H. Aminzadeh, R. Lotfi, K. Mafinezhad","doi":"10.1109/ISSOC.2008.4694856","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694856","url":null,"abstract":"Traditional design of low-dropout regulators offer the use of metal-insulator-metal (MIM) compensation capacitors to prevent instability in the absence of load capacitor with equivalent series resistance (ESR). In addition to area efficiency achieved by replacing these capacitors with MOS transistors, the location of implanted transfer function poles and zeros are adaptively changed according to the value of load current. The idea has been applied to stabilize a 1.2 V, 100 mA low-dropout regulator in a 0.18 mum CMOS n-well process. Using the proposed technique, the regulator meets stability with a small 100 pF MOS output capacitor and no ESR.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128350659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
RF transmitter architecture investigation for power efficient mobile WiMAX applications 节能移动WiMAX应用的射频发射机架构研究
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694883
Liang Rong, F. Jonsson, Lirong Zheng, M. Carlsson, Charlotta Hedenas
{"title":"RF transmitter architecture investigation for power efficient mobile WiMAX applications","authors":"Liang Rong, F. Jonsson, Lirong Zheng, M. Carlsson, Charlotta Hedenas","doi":"10.1109/ISSOC.2008.4694883","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694883","url":null,"abstract":"Wireless broadband digital communication systems with high spectral efficiency suffer from severe power efficiency problem. Peak-to-Average Power Ratio is reported up to 12dB for WiMAX 802.16e systems implementing OFDM IFFT-1024 and 64-QAM modulation. In this work, outphasing (LINC) and polar transmitter architectures are investigated and compared with direct conversion (DC) architecture. Complete system solution targeting 23dBm output power is evaluated. System level simulation result shows that, with linear power combiner, LINC consumes more power than DC if non-clipping modulation scheme used. And polar system has stringent 3 degree phase matching and 0.5 dB gain matching requirements to meet EVM and spectrum mask specifications.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130035171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimizing routing tables on systems-on-chip with Content-Addressable Memories 基于内容可寻址存储器的片上系统路由表优化
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694879
S. Stergiou, Jawahar Jain
{"title":"Optimizing routing tables on systems-on-chip with Content-Addressable Memories","authors":"S. Stergiou, Jawahar Jain","doi":"10.1109/ISSOC.2008.4694879","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694879","url":null,"abstract":"Routing tables are part of a critical subsystem of modern internet routers that controls the filtering and forwarding of packets. They are typically embedded in content-addressable memories which in this context behave as elaborated sum-of-products expression evaluators. In this work, we examine the applicability of exclusive-or sum-of-products expressions as an alternative routing table formulation and conclude that they provide significant and practical savings in CAM utilization.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115063351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1V current-mode filter in 65nm CMOS using capacitance multiplication 在65nm CMOS中使用电容倍增的1V电流模式滤波器
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694858
H. Uhrmann, H. Zimmermann
{"title":"A 1V current-mode filter in 65nm CMOS using capacitance multiplication","authors":"H. Uhrmann, H. Zimmermann","doi":"10.1109/ISSOC.2008.4694858","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694858","url":null,"abstract":"A new capacitance saving method for differential current-mode filter structures is presented. Especially filters with low cut-off frequencies need large capacitors, which comes along with large and expensive chip area. We show the opportunity to save chip-area in a 3rd-order current-mode Butterworth low-pass filter and enlarge the effective capacitance value by 30%. The proposed filter is designed to be in a transmit path in a software defined radio of a mixed-signal system on chip. It is developed and fabricated in low-power 65 nm CMOS and needs an active area of 215 mum times 215 mum. The supply voltage is 1 V at a current consumption of 9.6 mA. The filter reaches a third-order input intercept point of 1.6 mAp and a dynamic range of 73.8 dB at a cut-off frequency of 1 MHz.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114259704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network 在德布鲁因互连网络上实现软件无线电的灵活约束长度维特比解码器
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694861
Ganesh Garga, M. Alle, Keshavan Varadarajan, S. Nandy, H. Jamadagni
{"title":"Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network","authors":"Ganesh Garga, M. Alle, Keshavan Varadarajan, S. Nandy, H. Jamadagni","doi":"10.1109/ISSOC.2008.4694861","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694861","url":null,"abstract":"Building flexible constraint length Viterbi decoders requires us to be able to realize de Bruijn networks of various sizes on the physically provided interconnection network. This paper considers the case when the physical network is itself a de Bruijn network and presents a scalable technique for realizing any n-node de Bruijn network on an N-node de Bruijn network, where n < N. The technique ensures that the length of the longest path realized on the network is minimized and that each physical connection is utilized to send only one data item, both of which are desirable in order to reduce the hardware complexity of the network and to obtain the best possible performance.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114561825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FlexPath NP - A network processor architecture with flexible processing paths 一种具有灵活处理路径的网络处理器架构
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694869
Michael Meitinger, Rainer Ohlendorf, Thomas Wild, A. Herkersdorf
{"title":"FlexPath NP - A network processor architecture with flexible processing paths","authors":"Michael Meitinger, Rainer Ohlendorf, Thomas Wild, A. Herkersdorf","doi":"10.1109/ISSOC.2008.4694869","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694869","url":null,"abstract":"In this paper we present a FlexPath network processor implementation, a platform with flexible, reconfigurable processing paths for packet processing. The path decision is made in hardware based on a packetpsilas network application. Packets may be processed by a CPU or even completely in hardware. With our demonstrator the performance of different processing paths is shown for a scenario with simple IPv4 forwarding traffic mixed with IPSec packets. We show that flexible path selection significantly improves the systempsilas performance. The specific FlexPath concepts are also applicable to other NP architectures.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123647024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Implementation of W-CDMA slot synchronization on a reconfigurable System-on-Chip 可重构片上系统W-CDMA槽同步的实现
2008 International Symposium on System-on-Chip Pub Date : 2008-12-08 DOI: 10.1109/ISSOC.2008.4694868
F. Garzia, C. Brunelli, Carmelo Giliberto, Roberto Airoldi, J. Nurmi
{"title":"Implementation of W-CDMA slot synchronization on a reconfigurable System-on-Chip","authors":"F. Garzia, C. Brunelli, Carmelo Giliberto, Roberto Airoldi, J. Nurmi","doi":"10.1109/ISSOC.2008.4694868","DOIUrl":"https://doi.org/10.1109/ISSOC.2008.4694868","url":null,"abstract":"This paper describes the implementation of the slot synchronization of a W-CDMA receiver on a reconfigurable system. The system includes a general-purpose processor core with floating-point capabilities and a reconfigurable array. We mapped a 256-element correlation on the array and we evaluated its performance. The slot synchronization uses a large number of this correlations. The stand-alone correlation produces a speed-up of 70X when mapped on the reconfigurable core in comparison with the software implementation on a general-purpose RISC core. The slot synchronization based on this implementation gives a speed-up of 33X against an area overhead of 4X.","PeriodicalId":168022,"journal":{"name":"2008 International Symposium on System-on-Chip","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127742731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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