在65nm CMOS中使用电容倍增的1V电流模式滤波器

H. Uhrmann, H. Zimmermann
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引用次数: 2

摘要

提出了一种新的差分电流型滤波器结构的电容节省方法。特别是截止频率较低的滤波器,需要较大的电容,这就带来了大而昂贵的芯片面积。我们展示了在三阶电流模式巴特沃斯低通滤波器中节省芯片面积的机会,并将有效电容值扩大了30%。所提出的滤波器被设计在片上混合信号系统的软件定义无线电的传输路径上。它是在低功耗65nm CMOS上开发和制造的,需要215 μ m乘以215 μ m的有源面积。电源电压为1v,电流消耗为9.6 mA。在截止频率为1mhz时,滤波器的三阶输入截距点为1.6 mAp,动态范围为73.8 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 1V current-mode filter in 65nm CMOS using capacitance multiplication
A new capacitance saving method for differential current-mode filter structures is presented. Especially filters with low cut-off frequencies need large capacitors, which comes along with large and expensive chip area. We show the opportunity to save chip-area in a 3rd-order current-mode Butterworth low-pass filter and enlarge the effective capacitance value by 30%. The proposed filter is designed to be in a transmit path in a software defined radio of a mixed-signal system on chip. It is developed and fabricated in low-power 65 nm CMOS and needs an active area of 215 mum times 215 mum. The supply voltage is 1 V at a current consumption of 9.6 mA. The filter reaches a third-order input intercept point of 1.6 mAp and a dynamic range of 73.8 dB at a cut-off frequency of 1 MHz.
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