Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)最新文献_第7页

Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators 增加最低工作电压(VDDmin)与CMOS逻辑门的数量和实验验证高达1兆级环形振荡器

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393952

T. Niiyama, Piao Zhe, K. Ishida, M. Murakata, M. Takamiya, T. Sakurai

引用次数: 24

A 1-V piecewise curvature-corrected CMOS bandgap reference 一种1v分段曲率校正CMOS带隙基准

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393996

Li Jing-hu, Fu Yu-nan, Wang Yong-sheng

引用次数: 6

SOC designs in the energy conscious era 能源意识时代的SOC设计

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394001

Srikanth Jadcherla

{"title":"SOC designs in the energy conscious era","authors":"Srikanth Jadcherla","doi":"10.1145/1393921.1394001","DOIUrl":"https://doi.org/10.1145/1393921.1394001","url":null,"abstract":"Summary form only given. Many of us are aware of the impact of mobile and consumer era SOCs on Low Power Design. What is less known is the impact of proliferation in volumes unimaginable ever before and how that impacts already scarce energy resources in various parts of the world. Today, the energy consumption of installed semiconductors is responsible for more CO2 emissions than the entire airlines industry. Ironically, this problematic trend is being noticed not by the semiconductor industry itself, but by governments worldwide. Further, technology migration does not help combat this problem, it only makes it worse - leading to unprecedented regulatory pressures on the semiconductor industry. In parallel to this trend, lies the fact that semiconductor proliferation in developing economies comes with challenges in power generation and distribution - a fact that is fundamentally being altered by the advent of solar power and Direct DC power supply. This trend is amply supplemented by Power over Ethernet and Media convergence over Ethernet. All in all, the SOC/system of the future will look dramatically different in its architecture. How will all if these market forces impact the SOC designs of the next generation? How hard will it be to design and verify these SOCs? We try to identify these trends and their impact in this talk.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130340098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhancing beneficial jitter using phase-shifted clock distribution 利用相移时钟分布增强有益抖动

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393932

Dong Jiao, Jie Gu, P. Jain, C. Kim

引用次数: 8

Power-gating-aware high-level synthesis 功率门控高级合成

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393936

Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin

{"title":"Power-gating-aware high-level synthesis","authors":"Eunjoo Choi, Changsik Shin, Taewhan Kim, Youngsoo Shin","doi":"10.1145/1393921.1393936","DOIUrl":"https://doi.org/10.1145/1393921.1393936","url":null,"abstract":"A problem inherent in designing power-gated circuits is the overhead of the state-retention storage required to preserve the circuit state in standby mode. Reducing the amount of retention storage is known to be the most influential factor in minimizing the loss of the benefit (i.e. power saving) by power-gating. In this paper, we address a new problem of high-level synthesis with the objective of minimizing the size of retention storage to be used in the power-gated circuits. Specifically, we propose a complete design framework, called HLS-pg, that starts from the power-gating-aware scheduling, allocation, and controller synthesis down to the final circuit layout. The key contribution of the work is to solve the power-gating-aware scheduling problem, namely, scheduling operations that minimizes the number of retention registers required at the power-gating control step, while satisfying resource and latency constraints. In experiments on benchmark designs implemented in 65-nm CMOS technology, HLS-pg generates circuits with 27% less leakage current, with 6% less circuit area and wirelength, compared to the power-gated circuits produced by conventional high-level synthesis.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128700889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Next-generation power-aware design 下一代功耗感知设计

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393927

T. Sakurai

{"title":"Next-generation power-aware design","authors":"T. Sakurai","doi":"10.1145/1393921.1393927","DOIUrl":"https://doi.org/10.1145/1393921.1393927","url":null,"abstract":"Summary form only given. Reducing power is still the main interest in the recent integrated circuit designs. Some of the new low-power design approaches are covered in this talk. Three-dimensional stacking of chips is an effective way to reduce power by decreasing inter-chip communication energy. A low-power yet low-cost interconnection method among stacked chips is wireless communication by L-coupling and C-coupling. The recent advances in these proximity communication approaches are discussed. The other effective approach for achieving low power is to explore operations under ultra-low supply voltage. The effect of variation in the ultra-low operating supply voltage regime is discussed with measurement results. Other point of interest for power-aware systems is the source of energy. The limited access to the power source has been a limiter for the ubiquitous electronics to fly. Wireless transmission of power will offer new application scenes for ubiquitous electronics. The talk also covers an interesting yet exotic integrated circuit made of organic transistors and MEMS switches which acts as a wireless power transmission sheet and may provide a solution to last-meter problem of energy-net.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133763796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

PowerAntz: distributed power sharing strategy for network on chip PowerAntz:基于片上网络的分布式功率共享策略

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393968

Sumana Mandal, R. Mahapatra

引用次数: 0

Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies 具有可扩展电源电压和频率的低功耗短距离光电收发器前端设计

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393994

Xuning Chen, Gu-Yeon Wei, L. Peh

引用次数: 17

Variability of flip-flop timing at sub-threshold voltages 亚阈值电压下触发器时序的可变性

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393979

N. Lotze, M. Ortmanns, Y. Manoli

引用次数: 29

Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures 动态电压和频率缩放对GALS体系结构脆弱性的影响

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394016

N. Soundararajan, N. Vijaykrishnan, A. Sivasubramaniam

{"title":"Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures","authors":"N. Soundararajan, N. Vijaykrishnan, A. Sivasubramaniam","doi":"10.1145/1393921.1394016","DOIUrl":"https://doi.org/10.1145/1393921.1394016","url":null,"abstract":"Aggressive technology scaling is increasing the impact of soft errors on microprocessor reliability. Dynamic Voltage Frequency Scaling (DFVS) algorithms are conventionally studied from a performance per watt basis. But applying DVFS impacts reliability as well. Since DVFS affects the occupancy of different pipeline structures, they impact the soft error masking seen at the architectural level. Architectural Vulnerability Factors (AVF) captures this masking and in this work we study the impact of DVFS on AVF in a GALS environment. We show that the AVF of pipeline structures could vary by as much as 80% between different DVFS algorithms. Since AVF has a significant impact on the Mean Time To Failure (MTTF) of a system, these results indicate that when choosing a particular DVFS algorithm their reliability impact cannot be ignored. Hence we provide the Vulnerability Efficiency for the DVFS algorithms which captures their ability to optimize performance, power and reliability. Our results show that a Non-DVFS environment optimizes vulnerability efficiency better than any of the DVFS algorithms.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132330873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12