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Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)最新文献

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Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scaling 具有动态电压和频率缩放的电池感知稳压器调度同步优化
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394005
Youngjin Cho, Younghyun Kim, Yongsoo Joo, Kyungsoo Lee, N. Chang
{"title":"Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scaling","authors":"Youngjin Cho, Younghyun Kim, Yongsoo Joo, Kyungsoo Lee, N. Chang","doi":"10.1145/1393921.1394005","DOIUrl":"https://doi.org/10.1145/1393921.1394005","url":null,"abstract":"Energy-aware task scheduling significantly reduces the total energy required by a system to perform a particular job, by dynamically changing the clock frequency and supply voltage at which the CPU operates. But this causes significant fluctuation of the current drawn from the power source, so that no single voltage regulator can achieve satisfactory efficiency over the entire range of operating currents. We introduce a new method of high-level power management called dynamic voltage regulator scheduling (DRS), which overcomes the fundamental limitation of using a single voltage regulator. In a system equipped with DRS, heterogeneous voltage regulators are connected to a CPU through a multiplexer-type MOSFET switch. As the operating frequency and the supply voltage of the CPU vary, the most efficient voltage regulator is used to supply the power. We first describe a greedy method of achieving DRS, and then we progress to an integer linear programming (ILP) formulation, which simultaneously optimizes DRS together with dynamic voltage and frequency scaling (DVFS). We evaluate the performance of both greedy DRS and optimal DRS. Compared to conventional DVFS, greedy DRS saves an additional 5.4% to 14.6% of the total system energy; and optimal DRS saves an additional 11.5% to 15.5%.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122293014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning 采用米勒电容调谐的1.8/2.4 ghz双频cmos低噪声放大器
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393997
Depak Balemarthy, R. Paily
{"title":"A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning","authors":"Depak Balemarthy, R. Paily","doi":"10.1145/1393921.1393997","DOIUrl":"https://doi.org/10.1145/1393921.1393997","url":null,"abstract":"This paper describes an inductively source degenerated dual-band low noise amplifier (LNA) designed in a standard CMOS 0.18 μm TSMC process. The dual-band LNA can be tuned to 1.8-GHz and 2.4-GHz. The impedance matching is obtained at the required frequency bands using Miller-capacitance tuning. The designed LNA exhibits a gain of 18.2dB and 16.2dB and a noise figure of 5.0dB and 3.7dB at 1.8 and 2.4-GHz respectively. The LNA design is carried out using Mentor Graphics Eldo software.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129737539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Advances in low power verification 低功耗验证的进展
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393925
J. Bergeron
{"title":"Advances in low power verification","authors":"J. Bergeron","doi":"10.1145/1393921.1393925","DOIUrl":"https://doi.org/10.1145/1393921.1393925","url":null,"abstract":"Summary form only given. Low Power design has traditionally been the area of Implementation engineers. However, with more and more advanced SOCs having to adopt aggressive Power Management techniques, the verification of these architectures has become an explosive problem. This talk will focus on the basic technology shifts required in the arena of verification - in dynanamic, static and formal analysis, in the area of Verification Methodology, Languages and Protocols and in next generation automation flows. The talk will also highlight some of the unsolved problems of today's technology and potential areas for research/collaboration between academia and industry.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114374091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analytical results for design space exploration of multi-core processors employing thread migration 采用线程迁移的多核处理器设计空间探索的分析结果
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393981
Ravishankar Rao, S. Vrudhula, Krzysztof S. Berezowski
{"title":"Analytical results for design space exploration of multi-core processors employing thread migration","authors":"Ravishankar Rao, S. Vrudhula, Krzysztof S. Berezowski","doi":"10.1145/1393921.1393981","DOIUrl":"https://doi.org/10.1145/1393921.1393981","url":null,"abstract":"Migrating threads away from the hot cores in a multicore processor allows them to operate at up to higher speeds. While this technique has already attracted a lot of research effort, the majority of thread migration studies are simulation-based. Although they are valuable for micro-architectural level optimization, they require prohibitively long simulation times, and hence have limited value for early design space exploration. We derive closed form expressions for the steady-state throughput of a multicore processor that employs thread migration and throttling for thermal management. These expressions can be evaluated under a millisecond (vs days for cycle-accurate simulation), and allow designers greater flexibility in evaluating the trade-offs involved in implementing thread migration on-chip. We also developed a system-level power/thermal simulator that we used to validate the analytical results.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114791495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Full-system chip multiprocessor power evaluations using FPGA-based emulation 基于fpga仿真的全系统芯片多处理器功耗评估
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394010
A. Bhattacharjee, Gilberto Contreras, M. Martonosi
{"title":"Full-system chip multiprocessor power evaluations using FPGA-based emulation","authors":"A. Bhattacharjee, Gilberto Contreras, M. Martonosi","doi":"10.1145/1393921.1394010","DOIUrl":"https://doi.org/10.1145/1393921.1394010","url":null,"abstract":"The design process for chip multiprocessors (CMPs) requires extremely long simulation times to explore performance, power, and thermal issues, particularly when operating system (OS) effects are included. In response, our novel FPGA-based emulation methodology models a full CMP design including applications and an OS. Activity counters programmed into the cores feed per-component microarchitectural power models. These models achieve under 10% error compared to detailed gate-level simulations. Our method retains software flexibility, but offers up to 35x speedup compared to corresponding full-system software simulations. We present our approach by emulating a 2-core Leon3 cache-coherent multiprocessor running Linux and parallel benchmarks. In an example case study, our emulated system uses activity counts (a proxy for temperature) to guide process migration between the CMP cores. Overall, this paper's methodology makes possible detailed power and thermal studies of CMPs and their operating systems.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134430473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
A secure and low-energy logic style using charge recovery approach 采用电荷回收方法的安全、低能耗逻辑风格
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393990
Mehrdad Khatir, A. Moradi, A. Ejlali, M. Shalmani, M. Salmasizadeh
{"title":"A secure and low-energy logic style using charge recovery approach","authors":"Mehrdad Khatir, A. Moradi, A. Ejlali, M. Shalmani, M. Salmasizadeh","doi":"10.1145/1393921.1393990","DOIUrl":"https://doi.org/10.1145/1393921.1393990","url":null,"abstract":"The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high energy efficiency but also to achieve the resistance against side-channel attacks especially against differential power analysis attacks. Our approach is a modified version of a classical charge recovery logic style namely 2N-2N2P. Simulation results show a significant improvement in DPA-resistance level as well as in power consumption reduction in comparison with 2N-2N2P and other DPA-resistant logic styles.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115688489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Single stage static level shifter design for subthreshold to I/O voltage conversion 用于亚阈值到I/O电压转换的单级静态电平移位器设计
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393973
Yu-Shiang Lin, D. Sylvester
{"title":"Single stage static level shifter design for subthreshold to I/O voltage conversion","authors":"Yu-Shiang Lin, D. Sylvester","doi":"10.1145/1393921.1393973","DOIUrl":"https://doi.org/10.1145/1393921.1393973","url":null,"abstract":"A static subthreshold to I/O voltage level shifter is proposed. The proposed circuit employs a diode-connected pull-up transistor stack and a feedback structure to alleviate the drive strength requirement on the pull-down transistors. The proposed level shifter achieves less than 6 FO4 inverter delay under process and temperature variation when converting the input from 300 mV to 2.5 V. Compared to a conventional DCVS design, the new design consumes 8 times less power and is 10% faster under room temperature.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124369567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Optimal power and noise allocation for analog and digital sections of a low power radio receiver 低功率无线电接收机模拟和数字部分的最佳功率和噪声分配
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393993
K. Sankaragomathi, Manodipan Sahoo, S. Dwivedi, B. Amrutur, N. Bhat
{"title":"Optimal power and noise allocation for analog and digital sections of a low power radio receiver","authors":"K. Sankaragomathi, Manodipan Sahoo, S. Dwivedi, B. Amrutur, N. Bhat","doi":"10.1145/1393921.1393993","DOIUrl":"https://doi.org/10.1145/1393921.1393993","url":null,"abstract":"We determine the optimal allocation of power between the analog and digital sections of an RF receiver, while meeting the BER constraint. Unlike conventional RF receiver designs, we treat the SNR at the output of the analog front end (SNRAD) as a design parameter rather than a specification to arrive at this optimal allocation. We first determine the relationship of the SNRAD to the resolution and operating frequency of the digital section. We then use power models for the analog and digital sections to solve the power minimization problem. As an example, we consider a 802.15.4 compliant low-IF receiver operating at 2.4 GHz in 0.13 μm technology with 1.2 V power supply. We find that the overall receiver power is minimized by having the analog front end provide an SNR of 1.3 dB and the ADC and the digital section operate at 1-bit resolution with 18 MHz sampling frequency while achieving a power dissipation of 7 mW.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128298569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power reduction in on-chip interconnection network by serialization 通过串行化降低片上互连网络的功耗
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393974
A. Madan, B. Amrutur
{"title":"Power reduction in on-chip interconnection network by serialization","authors":"A. Madan, B. Amrutur","doi":"10.1145/1393921.1393974","DOIUrl":"https://doi.org/10.1145/1393921.1393974","url":null,"abstract":"We explore the use of serialization in on-chip buses for reducing interconnect energy. Serialization reduces wire density and hence the coupling capacitance between adjacent data bits. This enables higher data rates, thus making it possible to send multiple data bits on a single wire within a single clock cycle. Energy reduction is brought about as a result of the decreased coupling capacitance, however this is offset by increased size and number of repeaters to obtain higher speed. A critical delay exists above which serialization is more energy efficient. We find this critical delay for a 2:1 serialization by solving an optimization problem formulated as minimization of power with serialization factor (1 or 2), area, bandwidth and frequency as constraints, and having repeater size, number of repeaters, and wire dimensions as design variables. We find that for delays above 40% of minimum delay for the wire, double pumping is more energy efficient across a range of technology nodes and supply voltages and matches well with a simple analytical derivation.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130549966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Proactive temperature management in MPSoCs mpsoc的主动温度管理
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393966
A. Coskun, T. Simunic, K. Gross
{"title":"Proactive temperature management in MPSoCs","authors":"A. Coskun, T. Simunic, K. Gross","doi":"10.1145/1393921.1393966","DOIUrl":"https://doi.org/10.1145/1393921.1393966","url":null,"abstract":"Preventing thermal hot spots and large temperature variations on the die is critical for addressing the challenges in system reliability, performance, cooling cost and leakage power. Reactive thermal management methods, which take action after temperature reaches a given threshold, maintain the temperature below a critical level at the cost of performance, and do not address the temperature variations. In this work, we propose a proactive thermal management approach, which estimates the future temperature using regression, and allocates workload on a multicore system to reduce and balance the temperature to avoid temperature induced problems. Our technique reduces the hot spots and temperature variations significantly in comparison to reactive strategies.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"441 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115254955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 85
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