{"title":"A 1-V piecewise curvature-corrected CMOS bandgap reference","authors":"Li Jing-hu, Fu Yu-nan, Wang Yong-sheng","doi":"10.1145/1393921.1393996","DOIUrl":null,"url":null,"abstract":"A 1-V piecewise curvature-corrected CMOS bandgap reference (BGR) is proposed. It features in utilizing piecewise corrected current to a conventional first-order current-mode BGR. The corrected current is zero, exponential with temperature and proportional to the squared temperature in the lower, middle and upper temperature range (TR). Simulated results indicate that proposed BGR achieves temperature coefficient (TC) of 1.18ppm/°C in the TR of -30-130°C, power supply rejection ratio (PSRR) of -52dB and line regulation of 0.1mV/V in the supply range of 1-1.8V. The maximum power consumption is 29.5μW. It is designed in HJTC 0.18-μm n-well CMOS process.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1393921.1393996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A 1-V piecewise curvature-corrected CMOS bandgap reference (BGR) is proposed. It features in utilizing piecewise corrected current to a conventional first-order current-mode BGR. The corrected current is zero, exponential with temperature and proportional to the squared temperature in the lower, middle and upper temperature range (TR). Simulated results indicate that proposed BGR achieves temperature coefficient (TC) of 1.18ppm/°C in the TR of -30-130°C, power supply rejection ratio (PSRR) of -52dB and line regulation of 0.1mV/V in the supply range of 1-1.8V. The maximum power consumption is 29.5μW. It is designed in HJTC 0.18-μm n-well CMOS process.