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Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)最新文献

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Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension 通过制造后ISA扩展提高基于处理器的嵌入式系统的能源效率
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393987
Hamid Noori, Farhad Mehdipour, Koji Inoue, K. Murakami
{"title":"Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension","authors":"Hamid Noori, Farhad Mehdipour, Koji Inoue, K. Murakami","doi":"10.1145/1393921.1393987","DOIUrl":"https://doi.org/10.1145/1393921.1393987","url":null,"abstract":"Application-specific instruction set extension is an effective technique for reducing accesses to components such as on- and off-chip memories, register file and enhancing the energy efficiency. However, the addition of custom functional units to the base processor is required for supporting custom instructions, which due to the increase of manufacturing and design costs in new nanometer-scale technologies and shorter time-to-market, is becoming an issue. To address above issues, in our proposed approach, an optimized reconfigurable functional unit is used instead, and instruction set customization is done after chip-fabrication. Therefore, while maintaining the flexibility of a conventional microprocessor, the low-energy feature of customization is applicable. Experimental results show that the maximum and average energy savings are 67% and 22%, respectively for our proposed architecture framework.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134156770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power 以可靠性为中心的栅极尺寸，同时优化软错误率、延迟和功率
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393948
K. Bhattacharya, N. Ranganathan
{"title":"Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power","authors":"K. Bhattacharya, N. Ranganathan","doi":"10.1145/1393921.1393948","DOIUrl":"https://doi.org/10.1145/1393921.1393948","url":null,"abstract":"The reliability against transient faults poses a significant challenge due to technology scaling trends. Several circuit optimization techniques have been proposed in the literature for preventing soft errors in logic circuits. However, most approaches do not incorporate the effects of other design metrics like delay and power while optimizing the circuit for soft error protection. In this work, we develop a first order model of the soft error phenomenon in logic circuits and incorporate power and delay metrics to formulate a convex programming based reliability-centric gate sizing technique. The proposed algorithm has been implemented and validated on the ISCASS85 benchmarks. Experimental results indicate that our multi-objective optimization technique can achieve significant reductions in soft error rate with simultaneous optimization of delay and power.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129858831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Noninvasive leakage power tomography of integrated circuits by compressive sensing 基于压缩感知的集成电路无创泄漏功率层析成像
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394011
Davood Shamsi, P. Boufounos, F. Koushanfar
{"title":"Noninvasive leakage power tomography of integrated circuits by compressive sensing","authors":"Davood Shamsi, P. Boufounos, F. Koushanfar","doi":"10.1145/1393921.1394011","DOIUrl":"https://doi.org/10.1145/1393921.1394011","url":null,"abstract":"We introduce a new methodology for noninvasive post-silicon characterization of the unique static power profile (tomogram) of each manufactured chip. The total chip leakage is measured for multiple input vectors in a linear optimization framework where the unknowns are the gate leakage variations. We propose compressive sensing for fast extraction of the unknowns since the leakage tomogram contains correlations and can be sparsely represented. A key advantage of our approach is that it provides leakage variation estimates even for inaccessible gates. Experiments show that the methodology enables fast and accurate noninvasive extraction of leakage power characteristics.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115546400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Clock gating for power optimization in ASIC design cycle theory & practice 时钟门控在ASIC设计周期中功率优化的理论与实践
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394003
S. Jairam, M. Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, J. Rao
{"title":"Clock gating for power optimization in ASIC design cycle theory & practice","authors":"S. Jairam, M. Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, J. Rao","doi":"10.1145/1393921.1394003","DOIUrl":"https://doi.org/10.1145/1393921.1394003","url":null,"abstract":"In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with re-cent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend design space. We show that over 30% power savings in dynamic power can be achieved through this methodology subject to application scenarios of the design.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion 通过保持器插入减少MTCMOS电路的唤醒延迟和能量
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393942
Charbel J. Akl, M. Bayoumi
{"title":"Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion","authors":"Charbel J. Akl, M. Bayoumi","doi":"10.1145/1393921.1393942","DOIUrl":"https://doi.org/10.1145/1393921.1393942","url":null,"abstract":"A simple yet effective technique that aims at reducing the energy and latency overheads incurred during the wakeup period of MTCMOS circuits is presented in this paper. One or more high-Vth keepers are inserted in MTCMOS combinational logic to reduce the metastability time that causes excessive short circuit current during mode transition and to minimize spurious glitches at internal circuit nodes. Employing the proposed keeper insertion technique in a 16-bit MTCMOS adder, up to 17.5% average wakeup energy and 54.6% wakeup latency reductions are achieved with negligible runtime power and latency overheads, while maintaining the standby energy efficiency of the original MTCMOS design.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130276238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors O2C:在高性能有序微处理器中用于动态热管理的偶尔两周期操作
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393971
Swaroop Ghosh, J. Choi, P. Ndai, K. Roy
{"title":"O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors","authors":"Swaroop Ghosh, J. Choi, P. Ndai, K. Roy","doi":"10.1145/1393921.1393971","DOIUrl":"https://doi.org/10.1145/1393921.1393971","url":null,"abstract":"In this paper, we propose O2C, a novel non-speculative adaptive thermal management technique that reduces the temperature during die-overheating using supply voltage scaling, while maintaining the rated clock frequency. This is accomplished by (a) scaling down the supply voltage, (b) isolating and predicting the set of critical paths, (c) ensuring (by design) that they are activated rarely, and (d) getting around occasional delay failures (at reduced voltage during die-overheating) in these paths by two-cycle operations (assuming all standard operations are single-cycle). Two-cycle operation is achieved by stalling the pipeline for extra clock cycles whenever the set of critical paths are activated. The rare two-cycle operation results in a small decrease in IPC (instructions per cycle). Since called O2C maintains the rated clock frequency and does not require pipeline stalling during supply voltage ramp-up/ramp-down, it achieves high throughput in a thermally constrained environment. We applied called O2C to the integer execution units of an in-order superscalar pipeline. Standard full-chip Dynamic Voltage-Frequency Scaling (DVFS) is very effective in bringing down the temperature, however; it is associated with large throughput loss due to pipeline stalling and slow operating frequency during thermal management. We integrated \"O2C with standard DVFS\" (called O2Cα) to demonstrate that it can act as a \"first step\" before full-scale thermal management is required. Our simulations indeed reveal that called O2Cα policy can avoid the requirement of full-scale DVFS during execution of programs.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128513803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits 90nm亚阈值电路中体偏置晶体管变异性模型与环振荡频率的相关性验证
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393929
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
{"title":"Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits","authors":"H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye","doi":"10.1145/1393921.1393929","DOIUrl":"https://doi.org/10.1145/1393921.1393929","url":null,"abstract":"This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on measurement of a device array circuit in a 90 nm technology. The device array consists of P/NMOS transistors and ring oscillators. This work verifies the correlation between the variation model extracted from IV measurement results and oscillation frequencies, which means the transistor-level variation model is examined and confirmed in terms of circuit performance. We demonstrate that delay variations of subthreshold circuits are well characterized with two parameters - threshold voltage and subthreshold swing parameter. We reveal that body bias effect is a less statistical phenomenon and threshold voltage shift by body biasing can be modeled deterministically.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125611999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Energy harvesting photodiodes with integrated 2D diffractive storage capacitance 集成二维衍射存储电容的能量收集光电二极管
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393941
N. J. Guilar, E. Fong, Travis Kleeburg, D. Yankelevich, R. Amirtharajah
{"title":"Energy harvesting photodiodes with integrated 2D diffractive storage capacitance","authors":"N. J. Guilar, E. Fong, Travis Kleeburg, D. Yankelevich, R. Amirtharajah","doi":"10.1145/1393921.1393941","DOIUrl":"https://doi.org/10.1145/1393921.1393941","url":null,"abstract":"Integrating photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, low-cost energy harvesting wireless systems. To further explore the tradeoffs between optical efficiency and capacitive energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in TSMC's 90 nm CMOS technology. Transient effects from interfacing the photodiodes with switching regulators were examined. A quantitative comparison between 90 nm and 0.35 μm CMOS logic processes for energy harvesting capabilities was carried out. Measurements show an increase in power generation for the newer CMOS technology, however at the cost of reduced output voltage.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122848932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Hybrid dynamic thermal management based on statistical characteristics of multimedia applications 基于统计特性的多媒体应用的混合动态热管理
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394007
Inchoon Yeo, Eun Jung Kim
{"title":"Hybrid dynamic thermal management based on statistical characteristics of multimedia applications","authors":"Inchoon Yeo, Eun Jung Kim","doi":"10.1145/1393921.1394007","DOIUrl":"https://doi.org/10.1145/1393921.1394007","url":null,"abstract":"Recently multimedia applications become one of the most popular applications in mobile devices such as wireless phones, PDAs, and laptops. However, typical mobile systems are not equipped with cooling components, which eventually causes critical thermal deficiencies. Although many low-power and low-temperature multimedia playback techniques have been proposed, they failed to provide QoS (Quality of Service) while controlling temperature due to the lack of proper understanding of multimedia applications. We propose Hybrid Dynamic Thermal Management (HDTM) which exploits thermal characteristics of both multimedia applications and systems. Specifically, we model application characteristics as the probability distribution of the number of cycles required to decode a frame. We also improve existing system thermal models by considering the effect of work-load. This scheme finds an optimal clock frequency in order to prevent overheating with minimal performance degradation at runtime. The proposed scheme is implemented on Linux in a Pentium-M processor which provides variable clock frequencies. In order to evaluate the performance of the proposed scheme, we exploit three major codecs, namely MPEG-4, H.264/AVC and H.264/AVC streaming. Our results show that HDTM lowers the overall temperature by 15°C and the peak temperature by 20°C , while maintaining frame drop ratio under 0.2% compared to previous thermal management schemes such as feedback control DTM, Frame-based DTM and GOP-based DTM.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128111625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Design of dual threshold voltages asynchronous circuits 双阈值电压异步电路的设计
Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393970
B. Ghavami, H. Pedram
{"title":"Design of dual threshold voltages asynchronous circuits","authors":"B. Ghavami, H. Pedram","doi":"10.1145/1393921.1393970","DOIUrl":"https://doi.org/10.1145/1393921.1393970","url":null,"abstract":"This paper introduces a framework for the minimization of leakage power consumption of asynchronous circuits via using dual threshold voltages technique. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the circuit. We propose a heuristic method based on quantum genetic algorithm which finds the optimal high and low threshold voltage assignment. Experimental results are given for a number of 90 nm ISCAS benchmark circuits. From the experimental results, we show that the combination of asynchronous and multiple threshold voltage design techniques is an effective way to achieve low leakage power budget in high performance asynchronous circuits.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124374416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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