Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)最新文献_第5页

A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops 利用软边触发器进行电力管道优化设计的数学求解

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393935

M. Ghasemazar, B. Amelifard, Massoud Pedram

引用次数: 9

Optimal technology selection for minimizing energy and variability in low voltage applications 在低电压应用中最小化能量和可变性的最佳技术选择

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393930

Mingoo Seok, D. Sylvester, D. Blaauw

{"title":"Optimal technology selection for minimizing energy and variability in low voltage applications","authors":"Mingoo Seok, D. Sylvester, D. Blaauw","doi":"10.1145/1393921.1393930","DOIUrl":"https://doi.org/10.1145/1393921.1393930","url":null,"abstract":"Ultra Low voltage operation has recently drawn significant attention due to its large potential energy savings. However, typical design practices used for super-threshold operation are not necessarily compatible with the low voltage regime. Here, radically different guidelines may be needed since existing process technologies have been optimized for super-threshold operation. We therefore study the selection of the optimal technology in ultra low voltage designs to achieve minimum energy and minimum variability which are among foremost concerns. We investigate five industrial technologies, from 250 nm to 65 nm. We demonstrate that mature technologies are often the best choice in very low voltage applications, saving as much as ~1800X in total energy consumption compared to a poorly selected technology. In parallel, the effect of technology choice on variability is investigated, when operating at the energy optimal design point. The results show up to a 4X improvement in delay variation due to global process shift and mismatch when using the most advanced technologies despite their large variability at nominal Vdd.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132660386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 50

A multi-story power delivery technique for 3D integrated circuits 三维集成电路的多层供电技术

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393940

P. Jain, T. T. Kim, J. Keane, C. Kim

引用次数: 63

Caching for bursts (C-Burst): let hard disks sleep well and work energetically 突发缓存(C-Burst):让硬盘睡得好，精力充沛地工作

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393961

Feng Chen, Xiaodong Zhang

{"title":"Caching for bursts (C-Burst): let hard disks sleep well and work energetically","authors":"Feng Chen, Xiaodong Zhang","doi":"10.1145/1393921.1393961","DOIUrl":"https://doi.org/10.1145/1393921.1393961","url":null,"abstract":"High energy consumption has become a critical challenge in all kinds of computer systems. Hardware-supported Dynamic Power Management (DPM) provides a mechanism to save disk energy by transitioning an idle disk to a low-power mode. However, the achievable disk energy saving is mainly dependent on the pattern of I/O requests received at the disk. In particular, for a given number of requests, a bursty disk access pattern serves as a foundation for energy optimization. Aggressive prefetching has been used to increase disk access burstiness and extend disk idle intervals, while caching, a critical component in buffer cache management, has not been paid a specific attention. In the absence of cooperation from caching, the attempt to create bursty disk accesses would often be disturbed due to improper replacement decision made by energy unaware caching policies. In this paper, we present the design of a set of comprehensive energy-aware caching schemes, called C-Burst, and its implementation in Linux kernel 2.6.21. Our caching schemes leverage the 'filtering' effect of buffer cache to effectively reshape the disk access stream to a bursty pattern for energy saving. The experiments under various scenarios show that C-Burst schemes can achieve up to 35% disk energy saving with minimal performance loss.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"59 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114000001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

A tutorial on test power 关于测试功率的教程

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393984

V. Agrawal

{"title":"A tutorial on test power","authors":"V. Agrawal","doi":"10.1145/1393921.1393984","DOIUrl":"https://doi.org/10.1145/1393921.1393984","url":null,"abstract":"Both average power and peak power specifications of a circuit pose serious problems for the prevalent test methods like scan and built-in self-test. This tutorial discusses the problems and solutions for minimizing power dissipation in these test procedures. Hardware approaches and test vector optimization methods are outlined. Power-constrained testing of core-based systems is discussed. Finally, an open problem of finding an efficient test for verifying the power specification of a system is formulated. Today's electronic systems are complex, fast, and energy efficient. Power is a circuit design criteria, added to the previous list of area, delay and testability. Controlling test power and minimizing test time requires tradeoffs. Design for testability methods like scan and random-pattern self-test use non-functional test inputs that must conform to circuit specifications on average power (energy consumption) and peak power. Test power has thus become an active area of research, innovation and practice. Electronic circuits should dissipate no more power or energy than they are designed for. In testing of circuits cost and quality are the requirements and high fault coverage can lead to long, often nonfunctional, test sequences. Such tests generate substantially higher signal activity and can potentially cause an otherwise good circuit to fail due to excessive power dissipation. Tests are, therefore, run at a slower speed, incurring longer test time and higher test cost. This extra cost of testing does not completely solve the test power problem. The slow speed test can contain high activity vectors that would cause excessive supply current surges. Once again a perfectly good circuit can potentially fail during test due to conditions such as power droop, ground bounce and hot spots.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131062739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Expected system energy consumption minimization in leakage-aware DVS systems 泄漏感知分布式交换机系统中期望系统能耗最小化

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394006

Jian-Jia Chen, L. Thiele

引用次数: 36

Dynamic virtual ground voltage estimation for power gating 电源门控的动态虚拟地电压估计

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393934

Hao Xu, R. Vemuri, W. Jone

引用次数: 6

On leakage currents: sources and reduction for transistors, gates, memories and digital systems 关于泄漏电流:晶体管，栅极，存储器和数字系统的源和减少

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1394014

W. Nebel, D. Helms

引用次数: 0

Variation-aware gate sizing and clustering for post-silicon optimized circuits 后硅优化电路的变化感知门尺寸和聚类

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393949

Cheng Zhuo, D. Blaauw, D. Sylvester

{"title":"Variation-aware gate sizing and clustering for post-silicon optimized circuits","authors":"Cheng Zhuo, D. Blaauw, D. Sylvester","doi":"10.1145/1393921.1393949","DOIUrl":"https://doi.org/10.1145/1393921.1393949","url":null,"abstract":"As technology is aggressively scaled, nano-regime VLSI designs are becoming increasingly susceptible to process variations. Unlike pre-silicon optimization, post-silicon techniques can tune the individual die to better meet the power-delay constraints. This paper proposes a variation-aware methodology for the simultaneous gate sizing and clustering for post-silicon tuning with adaptive body biasing. The proposed methodology uses an accurate table look-up model and fully explores the interaction between gate sizing and optimal body bias based clustering. In addition, it is suitable for industrial test cases with tens of thousands gates. Our optimization methodology includes a body bias distribution alignment strategy to mitigate the impact of critical gates. In this way, the cluster's body bias voltage is not simply determined by only a few critical gates. We also prove the linear dependence between the mean of the body bias probability distribution and the gate size. Based on this, we further investigate a simultaneous sizing and re-clustering algorithm for better leakage savings. A circuit re-balancing and gate snapping scheme is then suggested to map the solution to a standard cell library. Compared with arecently-reported method, the proposed methodology can obtain on average 25.5% leakage saving at nearly the same run time.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129412205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Power management from cores to datacenters: where are we going to get the next ten-fold improvements? 从核心到数据中心的电源管理:我们将在哪里获得下一个十倍的改进?

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) Pub Date : 2008-08-11 DOI: 10.1145/1393921.1393959

Parthasarathy Ranganathan

引用次数: 1