1978 International Electron Devices Meeting最新文献

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Carrier recombination in heavily doped planar diodes 重掺杂平面二极管中的载流子复合
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189420
G. Possin, C. Kirkpatrick
{"title":"Carrier recombination in heavily doped planar diodes","authors":"G. Possin, C. Kirkpatrick","doi":"10.1109/IEDM.1978.189420","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189420","url":null,"abstract":"A process is described which produces a shallow pn junction device with heavy surface doping and very high collection efficiency. Electron beam techniques were used to measure collection efficiency as a function of depth and to modulate the surface recombination velocity through an MOS capacitor fabricated on the diode. The results of these studies indicate that surface recombination is the dominant effect on carrier loss.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114934226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Anomalous drain current in n-MOSFET's and its suppression by deep ion implantation n-MOSFET异常漏极电流及其深离子注入抑制
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189461
H. Nihira, M. Konaka, H. Iwai, Y. Nishi
{"title":"Anomalous drain current in n-MOSFET's and its suppression by deep ion implantation","authors":"H. Nihira, M. Konaka, H. Iwai, Y. Nishi","doi":"10.1109/IEDM.1978.189461","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189461","url":null,"abstract":"Effects of the deep ion implantation on the characteristics of the short channel n-MOSFET have been investigated by two-dimensional numerical analysis and verified experimentally. By the analysis, it has been found that the anomalous drain current which flows in the relatively deep region between the source and the drain has been effectively suppressed by the deep ion implantation of acceptor impurities into the channel region. Structure of short channel n-MOSFET with deep ion-implanted layer has been optimized by computer simulation to suppress the anomalous drain current. Experimentally, the low and steep subthreshold current characteristics have been obtained by deep ion implantation for short channel n-MOSFETs with LEFF= 1.2µm. Furthermore, the back gate bias dependence of the threshold voltage of the implanted short channel device can be made almost likely to that of the unimplanted long channel device.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117250668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Effects of channel potential modulation in narrow channel CCD shift registers 窄通道CCD移位寄存器中通道电位调制的影响
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189494
K. Venkateswaran
{"title":"Effects of channel potential modulation in narrow channel CCD shift registers","authors":"K. Venkateswaran","doi":"10.1109/IEDM.1978.189494","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189494","url":null,"abstract":"Channel potential modulation due to narrow width effects is shown to create undesired voltage barriers at the corner turn of CCD Serial Parallel Serial Shift Registers. A scheme is shown to measure this barrier accurately and estimate the trapped charge. Experimentally measured trapped charge agrees with the estimated trapped charge within 65%. The accuracy is being limited by the accuracy to which the trapping area can be estimated.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process 利用外延埋层工艺防止CMOS集成电路锁存的分析
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189394
D. Estreich, A. Ochoa, R. Dutton
{"title":"An analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process","authors":"D. Estreich, A. Ochoa, R. Dutton","doi":"10.1109/IEDM.1978.189394","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189394","url":null,"abstract":"The use of a p+buried layer beneath the p-well in CMOS is evaluated for controlling latch-up (parasitic SCR action). It is shown that this structure typically reduces the parasitic npn transistor's current gain by two orders of magnitude. The npn gain reduction is the principal mechanism for latch-up control. The npn has been studied using STRAP to numerically solve the transport equations. These simulations show the npn current gain to be primarily governed by the base-retarding field arising from the impurity gradient of the outdiffusing buried layer. A new wide-base lateral pnp model has been developed to accurately model the field enhancement of the parasitic lateral pnp's current gain. Experimental confirmation of the lateral pnp model is given.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130488595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
Prospects for M-I-M tunneling device displays M-I-M隧道装置显示器的前景
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189402
S. Mccarthy, J. Lambe
{"title":"Prospects for M-I-M tunneling device displays","authors":"S. Mccarthy, J. Lambe","doi":"10.1109/IEDM.1978.189402","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189402","url":null,"abstract":"Recently we reported the discovery of a new way of generating light from a solid-state thin-film structure","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130662273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design trade-offs in Schottky-base I2L—An advanced bipolar technology 肖特基基极I2L—一种先进的双极技术
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189388
A. Bahraman, S. Chang
{"title":"Design trade-offs in Schottky-base I2L—An advanced bipolar technology","authors":"A. Bahraman, S. Chang","doi":"10.1109/IEDM.1978.189388","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189388","url":null,"abstract":"This paper describes a novel bipolar technology, the Schottky-Base I2L, which offers significant advantages in terms of packing density, device performance, and reduced LSI circuit complexity as compared to conventional I2L designs. A pnp transistor fabricated in an n-epitaxial layer on a p+substrate forms the active switch for this design. Current source to the pnp is provided by an npn transistor. Schottky diodes are formed on the pnp base which is merged with the npn (injector) collector. Hence, the basic logic gate in this design is a multi-input, multi-output NAND gate. Because an n-on-p type structure is used, TTL, STTL, or ECL circuits can be made readily available on chip. Design trade-offs for optimizing the speed-power performance are described. Experimental data on a test chip indicate pnp current gain of ∼80 and a minimum delay of 10 ns of the SBI2L gate using 7.5 µm minimum linewidths.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123227691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Crossed-field guns analyzed on a deformable mesh 在可变形网格上分析交叉场炮
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189380
R. True
{"title":"Crossed-field guns analyzed on a deformable mesh","authors":"R. True","doi":"10.1109/IEDM.1978.189380","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189380","url":null,"abstract":"The principles of a method for the solution of electron optics problems in crossed electric and magnetic fields are described in this paper. The numerical procedure makes possible design and evaluation of crossed-field guns and focusing systems with a high degree of accuracy and resolution. Unlike other procedures, the space within the problem boundaries is filled with a computer-generated network of irregular triangles resembling a stretched fishnet on which Poisson's equation is solved. A novel approach is used in the near-cathode region leading to a substantial improvement in the accuracy of results in general.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A precise model of the transient response of MNOS memory capacitors MNOS存储电容器瞬态响应的精确模型
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189346
M. Powell, L. Jelsma
{"title":"A precise model of the transient response of MNOS memory capacitors","authors":"M. Powell, L. Jelsma","doi":"10.1109/IEDM.1978.189346","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189346","url":null,"abstract":"An accurate one-dimensional model of the metal-silicon nitride-silicon dioxide-silicon (MNOS) capacitor is presented. The numerical solution technique uses space and time discretization to implicitly solve the carrier current equations in the insulators and the partial differential equations that describe the static and dynamic carrier distributions in the silicon. Avalanche carrier generation and avalanche carrier injection mechanisms are included. The improved understanding of the physical behavior that ensues is used to design a fast programming transient (<1 microsecond) for the MNOS capacitor with a silicon dioxide thickness of 50 Å.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121689687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nitride-based passivation of GaAs for reduced surface state density 氮基钝化降低表面态密度
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189487
T. Hariu, N. Suzuki, K. Matsushita, Y. Shibata
{"title":"Nitride-based passivation of GaAs for reduced surface state density","authors":"T. Hariu, N. Suzuki, K. Matsushita, Y. Shibata","doi":"10.1109/IEDM.1978.189487","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189487","url":null,"abstract":"Nitride-based passivation of GaAs has been intended. Gallium oxy-nitride film was deposited by reactive sputtering with optimum oxygen incorporation into the film for the non-dispersive behavior of capacitance of the insulator film itself. The removal of native oxide from GaAs surface by sputter-etching with nitrogen resulted in the disappearance of anomalous frequency dispersion in the accumulation region of n-GaAs MIS structure, which is observed with native oxide deposited by anodic oxidation in electrolyte or gas plasma, and in the interface state density of the order of 1011cm-2eV-1.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114845031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GaAs OM CVD MESFET 加斯CVD CVD药房
1978 International Electron Devices Meeting Pub Date : 1900-01-01 DOI: 10.1109/IEDM.1978.189517
H. Morkoç, J. Andrews, V. Abei
{"title":"GaAs OM CVD MESFET","authors":"H. Morkoç, J. Andrews, V. Abei","doi":"10.1109/IEDM.1978.189517","DOIUrl":"https://doi.org/10.1109/IEDM.1978.189517","url":null,"abstract":"Al gate self aligned schottky barrier field effect transistors having gate dimensions of 1.5µ × 300µ and a channel length of 3µ were fabricated in epitaxial layers grown by organometallic chemical vapor deposition. The layers with a net carrier concentration of 1.4 × 1017cm-3were grown at 730°C. The devices exhibited a maximun dc transconductance (gm) of about 30 mmhos. The gmdegradation near the substrate interface appeared to be less than the comparable unbuffered vapor phase epitaxy (VPE) layers. The velocity profile into the active channel layer deduced from the dc performance of the devices indicated an average electron velocity of 1.3 × 107cm/sec which is the same as VPE material. The velocity degraded region was confined to within about 350 Å of the interface. This compares with about 500 Å in the unbuffered and about 200 Å in the buffered VPE material. A maximum available microwave gain of 10 dB and a noise figure of 3 dB with an associated gain of 5 dB at 8 GHz were measured. Those results are excellent considering the gate length of 1.5µ. Small-signal scattering parameters were measured and the equivalent circuit parameters were calculated. Devices having 0.5µ × 140µ gate dimensions are currently being fabricated. Any results on 0.5µ gate devices,and the performance of 1.5µ gate devices will be discussed. In the light of the above results, it is concluded that the OM-CVD technique may be capable of producing high quality FET material much faster than VPE and at a lower cost.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127764763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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