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Energy Efficient Home Gateway Based on User Service Traffic in Always-On Home Network Environment 家庭网络环境下基于用户业务流量的节能家庭网关
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.34
Wan-ki Park, Chang-Sic Choi, Haeryong Lee, Kwang-Roh Park
{"title":"Energy Efficient Home Gateway Based on User Service Traffic in Always-On Home Network Environment","authors":"Wan-ki Park, Chang-Sic Choi, Haeryong Lee, Kwang-Roh Park","doi":"10.1109/ENICS.2008.34","DOIUrl":"https://doi.org/10.1109/ENICS.2008.34","url":null,"abstract":"Home gateway (HG) is a device that connects multiple home network devices to an access network. The HG is to be always in operating state for providing any requested digital home services without suspension and user's waiting because these services can be started at any time, by any device and from any network. Furthermore, most home network devices are also required to be ready to operate at any time in the digital home environment. We call this characterized digital home network by 'always-on home network'. The characteristic of the 'always-on' in home network environment gives rise to consume more electrical power. In this paper, we propose a novel scheme to reduce the power consumed by a HG and the architecture to implement the proposed HG. The proposed scheme uses sleep and wake-up mechanism based on existence of real data traffic for user service. In the proposed scheme, almost hardware components of the HG are working, power-on, only in the period that some user service traffic is in the proposed HG; wake-up state or normal stat. On the other hand, some hardware components such as network protocol agent (NPA) with low power consumption are working in the period of no user service traffic. The NPA controls these sleep and wake-up for the proposed HG with cooperating with CPU.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"145 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131456855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 3-Mode Switched-Gain Low Noise Amplifier for Wireless Bands Applications Using an MMIC Technology 使用MMIC技术的无线频段应用的3模式开关增益低噪声放大器
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.27
M. Dousti, F. Eshghabadi, F. Temcamani, B. Delacressoniere, J. Gautier
{"title":"A 3-Mode Switched-Gain Low Noise Amplifier for Wireless Bands Applications Using an MMIC Technology","authors":"M. Dousti, F. Eshghabadi, F. Temcamani, B. Delacressoniere, J. Gautier","doi":"10.1109/ENICS.2008.27","DOIUrl":"https://doi.org/10.1109/ENICS.2008.27","url":null,"abstract":"This paper describes a 2.4 GHz single-ended switched gain low noise amplifier (SG-LNA) in a 0.35 mum SiGe BiCMOS process. In the design, specific architecture decisions were made in consideration of system-on-chip implementation. The architecture profits from a two cascode stage topology with a shunt resistive feedback in the first cascade-topology stage. The SG-LNA achieved a maximum small signal gain of 34.3 dB within input 1-dB compression point (ICP1dB) of -22 dBm in high-gain mode (HGM), a gain of 25.4 dB within ICP1dB of -13.8 dBm in medium-gain mode (MGM) , and a minimum gain of 18.3 dB within ICP1dB of -6.8 dBm in low-gain mode (LGM). The noise figures (NF) are 2.9 dB, 5.5 dB and 5.9 dB in HGM, MGM and LGM, respectively. Because of using a Common-Gate topology as an active input matching, the SG-LNA presented a good input and output return losses in all modes. All biases applied are active. The SG-LNA consumes a maximum DC current of 42 mA from a 3.3 volt DC supply.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129993357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Chromatic Modelling in Liquid Crystal Films for Ultrasonic Thermography 超声热成像液晶膜的彩色建模
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.14
G. A. López, A. Valentino, Arturo Vera, L. Leija
{"title":"Chromatic Modelling in Liquid Crystal Films for Ultrasonic Thermography","authors":"G. A. López, A. Valentino, Arturo Vera, L. Leija","doi":"10.1109/ENICS.2008.14","DOIUrl":"https://doi.org/10.1109/ENICS.2008.14","url":null,"abstract":"Several methods for the acquisition of bidimensional thermal images in acoustic fields produced by ultrasonic transducers for therapy have been described. A low cost technique used for the characterisation of ultrasonic therapy equipment consists in placing a thermochromic liquid crystal (TLC) film in a cross-section of the ultrasonic beam, forming a colorful image of the temperature distribution. This method gives information about the whole thermal pattern, which is related to intensity of ultrasound, offering a qualitative measurement. The present paper describes the acquisition of a sequence of thermal images in TLC films for the temperature range from 35degC to 40degC and digital image processing (DIP) used in order to get the mathematical model of the monotonic relation between temperature and color to get the quantitative measurement of the rise in temperature for future application in ultrasonic thermography.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"214 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134495962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Handel-C Implementation of a Computationally Intensive Problem in GF(3) GF(3)中一个计算密集型问题的Handel-C实现
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.18
J. Libby, J. Lutes, K. Kent
{"title":"A Handel-C Implementation of a Computationally Intensive Problem in GF(3)","authors":"J. Libby, J. Lutes, K. Kent","doi":"10.1109/ENICS.2008.18","DOIUrl":"https://doi.org/10.1109/ENICS.2008.18","url":null,"abstract":"Computing the irreducible and primitive polynomials under GF(3) is a computationally intensive task. A hardware implementation of this algorithm should prove to increase performance, reducing the time needed to perform the computation. Previous work explored the viability of a co-designed approach to this problem and this work continues addressing the problem by moving the entire algorithm into hardware. Handel-C was chosen as the hardware description language for this work due to its similarities with ANSI C used in the software implementation.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124236418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New Technologies for Improving the High Frequency Performance of AlGaN/GaN High Electron Mobility Transistors 提高AlGaN/GaN高电子迁移率晶体管高频性能的新技术
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.36
J.W. Chung, E. Piner, J. C. Roberts, T. Palacios
{"title":"New Technologies for Improving the High Frequency Performance of AlGaN/GaN High Electron Mobility Transistors","authors":"J.W. Chung, E. Piner, J. C. Roberts, T. Palacios","doi":"10.1109/ENICS.2008.36","DOIUrl":"https://doi.org/10.1109/ENICS.2008.36","url":null,"abstract":"In this paper, we have used a combination of physical analysis, numerical simulation and experimental work to overcome some of the main challenges in AlGaN/GaN high electron mobility transistors (HEMTs) for high frequency applications. In spite of their excellent material properties, GaN-based HEMTs are still below the theoretical predictions in their high frequency performance. If the frequency performance could be improved, the superior breakdown characteristics of nitride semiconductors would make these devices the best option for power amplifiers at Ka and even W band frequencies. To achieve this goal, we have first identified some of the critical parameters that limit the high frequency performance of AlGaN/GaN HEMTs and we have demonstrated several technologies to increase the performance. Some of these technologies include deep-submicron T-gate technology, thin-body GaN HEMTs, and advanced drain delay engineering.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123531604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Nanoscale Triple Material Double Gate (TM-DG) MOSFET for Improving Short Channel Effects 改善短沟道效应的纳米三材料双栅极MOSFET
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.33
P. Razavi, A. Orouji
{"title":"Nanoscale Triple Material Double Gate (TM-DG) MOSFET for Improving Short Channel Effects","authors":"P. Razavi, A. Orouji","doi":"10.1109/ENICS.2008.33","DOIUrl":"https://doi.org/10.1109/ENICS.2008.33","url":null,"abstract":"In this paper, a novel double-gate (DG) MOSFET in which the top and bottom gates consist of three laterally contacting material with different work functions is proposed. Using two-dimensional (2-D) device simulation, improvement of short channel effects such as drain-induced barrier lowering (DIBL), hot-carrier effects and channel length modulation (CLM) are investigated and compared with the dual material double-gate MOSFET and conventional DG MOSFET. This structure exhibits significantly improved short channel effects (SCEs) when compared with the conventional DG MOSFET.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127462775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Joint Optimal Detection of Ordering SIC ZF and SIC ZF MAP for V-BLAST/STBC Wireless Communication Systems V-BLAST/STBC无线通信系统中SIC ZF和SIC ZF MAP排序的联合最优检测
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.24
J. H. Chong, S. Khatun, N. Noordin, B. Ali, M. J. Syed
{"title":"Joint Optimal Detection of Ordering SIC ZF and SIC ZF MAP for V-BLAST/STBC Wireless Communication Systems","authors":"J. H. Chong, S. Khatun, N. Noordin, B. Ali, M. J. Syed","doi":"10.1109/ENICS.2008.24","DOIUrl":"https://doi.org/10.1109/ENICS.2008.24","url":null,"abstract":"In this paper, we consider a V-BLAST/STBC wireless communication architecture, which integrates Alamouti space-time block codes (STBC) layer with vertical Bell-labs layered space-time (V-BLAST) layer, in MIMO wireless communication system with four transmitter and three receiver antennas over Rayleigh flat-fading channel. We propose an algorithm, which combines the algorithm of successive interference cancellation zero-forcing (SIC ZF) and successive interference cancellation zero-forcing with maximum a posteriori probability (SIC ZF MAP). The proposed algorithm (SIC ZF / ZF MAP) reduces the complexity if compared with the algorithm of SIC ZF MAP alone. Simulation results show the symbol error rate performance degradation of the proposed algorithm is small compared to SIC ZF MAP detection.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131181655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Switched Current 12-Bit Capacity to Digital Delta-Sigma Modulator 开关电流12位容量到数字δ - σ调制器
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.16
M. Pavlík, J. Haze, R. Vrba
{"title":"Switched Current 12-Bit Capacity to Digital Delta-Sigma Modulator","authors":"M. Pavlík, J. Haze, R. Vrba","doi":"10.1109/ENICS.2008.16","DOIUrl":"https://doi.org/10.1109/ENICS.2008.16","url":null,"abstract":"This paper describes the design of the proposed capacity to digital converter. Some important simulations of the converter's behavior are presented as well. For capacity value processing second order delta-sigma modulator with input adjusting circuitry was used. The switched current (SI) technique was used in the proposal. It brings small dimensions of the chip and easy integration into the digital circuitry.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Microsensors for Partial Discharge 局部放电用微传感器
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.17
H. Tomas, P. Michal
{"title":"Microsensors for Partial Discharge","authors":"H. Tomas, P. Michal","doi":"10.1109/ENICS.2008.17","DOIUrl":"https://doi.org/10.1109/ENICS.2008.17","url":null,"abstract":"For longer service life and better reliability of high voltage under stressed parts or of such whole systems, facilities for deep investigation are necessary. Extremely small microsensors which can be integrated during the production inside measured object like high voltage transformers, drivers or high voltage parts of PCB's are, can serve us valued information about discharge activity during whole service life.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116781688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Geometry Optimization in Basic CMOS Cells for Improved Power, Leakage, and Noise Performances 基本CMOS电池的几何优化以改善功率、泄漏和噪声性能
2008 International Conference on Advances in Electronics and Micro-electronics Pub Date : 2008-09-29 DOI: 10.1109/ENICS.2008.26
J. Castro, A. Acosta, M. Vesterbacka
{"title":"Geometry Optimization in Basic CMOS Cells for Improved Power, Leakage, and Noise Performances","authors":"J. Castro, A. Acosta, M. Vesterbacka","doi":"10.1109/ENICS.2008.26","DOIUrl":"https://doi.org/10.1109/ENICS.2008.26","url":null,"abstract":"The rising demand for portable system is increasing the importance of low power as a design consideration. In this sense, leakage power is increasing much faster than dynamic power at smaller dimensions. Peak values of supply current are related to noise injected into the substrate and/or propagated through supply network, limiting the performances of the sensitive analog and RF portions of mixed-signal circuits. This paper analyses how these three aspects, dynamic power, leakage power and peak power, can be considered together, optimizing the sizing and design of basic cells, with a reduced degradation in performances. The suited sizing of basic cells, show the benefits of the proposed technique, validated through simulation results on 130 nm nand, nor and inverter cells.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116940422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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