{"title":"开关电流12位容量到数字δ - σ调制器","authors":"M. Pavlík, J. Haze, R. Vrba","doi":"10.1109/ENICS.2008.16","DOIUrl":null,"url":null,"abstract":"This paper describes the design of the proposed capacity to digital converter. Some important simulations of the converter's behavior are presented as well. For capacity value processing second order delta-sigma modulator with input adjusting circuitry was used. The switched current (SI) technique was used in the proposal. It brings small dimensions of the chip and easy integration into the digital circuitry.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Switched Current 12-Bit Capacity to Digital Delta-Sigma Modulator\",\"authors\":\"M. Pavlík, J. Haze, R. Vrba\",\"doi\":\"10.1109/ENICS.2008.16\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design of the proposed capacity to digital converter. Some important simulations of the converter's behavior are presented as well. For capacity value processing second order delta-sigma modulator with input adjusting circuitry was used. The switched current (SI) technique was used in the proposal. It brings small dimensions of the chip and easy integration into the digital circuitry.\",\"PeriodicalId\":162793,\"journal\":{\"name\":\"2008 International Conference on Advances in Electronics and Micro-electronics\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-09-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Conference on Advances in Electronics and Micro-electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ENICS.2008.16\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Advances in Electronics and Micro-electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ENICS.2008.16","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Switched Current 12-Bit Capacity to Digital Delta-Sigma Modulator
This paper describes the design of the proposed capacity to digital converter. Some important simulations of the converter's behavior are presented as well. For capacity value processing second order delta-sigma modulator with input adjusting circuitry was used. The switched current (SI) technique was used in the proposal. It brings small dimensions of the chip and easy integration into the digital circuitry.
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