Jesús Lázaro, S. Abejon, A. Astarloa, F. Chamorro, U. Bidarte
{"title":"SoPC Implementation of the TP-KNX Protocol for Domotic Applications","authors":"Jesús Lázaro, S. Abejon, A. Astarloa, F. Chamorro, U. Bidarte","doi":"10.1109/ENICS.2008.9","DOIUrl":"https://doi.org/10.1109/ENICS.2008.9","url":null,"abstract":"This paper presents a System-on-Programmable-Chip(SoPC) implementation of the KNX communication standard. KNX is a standardized communication protocol for the automation of homes and buildings. It is an open international standard. This means that any company can freely build new devices to be controlled using the standard. ASoPC implementation of the standard allows for applications of increased complexity while at the same time, reduces the time-to market-by the use of core-based design methodology.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134276370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I.O. Lertxundi, I. Díez, G. A. Aramendía, J. E. Marañon
{"title":"Inertial Events Identification Using Neural Networks in Railway Environments","authors":"I.O. Lertxundi, I. Díez, G. A. Aramendía, J. E. Marañon","doi":"10.1109/ENICS.2008.28","DOIUrl":"https://doi.org/10.1109/ENICS.2008.28","url":null,"abstract":"Global positioning system (GPS) resolves railway vehicles location most of the operation time. But what happens when those vehicles are near to critical points, as rail track changes, where more precision is needed? This paper presents a possible solution using inertial sensors and neural networks to find out patterns of railway changes among the inertial sensors' signal. The main objective of this investigation is to determine whether is possible or not to design a neural network capable of identifying or classifying the inertial patterns resulting from the trainpsilas railway changes.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122885025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Aliaga, R. Gadea, R. Colom, J. Monzó, C. Lerche, J. Martinez, A. Sebastiá, F. Mateo
{"title":"Multiprocessor SoC Implementation of Neural Network Training on FPGA","authors":"R. Aliaga, R. Gadea, R. Colom, J. Monzó, C. Lerche, J. Martinez, A. Sebastiá, F. Mateo","doi":"10.1109/ENICS.2008.22","DOIUrl":"https://doi.org/10.1109/ENICS.2008.22","url":null,"abstract":"Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for greater precision and flexibility in the structure of the networks to be trained with no need for device reconfiguration, and parallelism is achieved by the use of a large number of processing units. Design limitations are discussed, and preliminary results are presented on the performance of the system on an Altera DE2-70 development board.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115301559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yong-Seo Koo, Kwang-Yeob Lee, Jae-Seok Kwack, J. Won, Kui-Dong Kim
{"title":"The Design of Bi-CMOS LVDS Output Buffer with ESD Protection Circuit Using 90nm CMOS Technology","authors":"Yong-Seo Koo, Kwang-Yeob Lee, Jae-Seok Kwack, J. Won, Kui-Dong Kim","doi":"10.1109/ENICS.2008.23","DOIUrl":"https://doi.org/10.1109/ENICS.2008.23","url":null,"abstract":"This paper presents the design of novel LVDS (Low-Voltage-Differential-Signaling) output buffer for Gb/sper-pin operation using 90 nm CMOS technology. The proposed LVDS driver is designed to reduce chip area, using a novel bipolar transistor switch. The proposed LVDS transmitter is operated at 1.8 V low-power supply. Its maximum data rate is 2.8 Gb/s approximately. Also, the new structural ESD (Electro-Static Discharge) protection device is designed to improve the proposed LVDS driver's ESD protection performance. The proposed device can reduce latch-up phenomenon in normal operating condition. In the measurement result, the proposed ESD clamp has trigger voltage of 3.7 V and holding voltage of 2.3 V. The robustness of the LVDS driver with proposed ESD protection has measured to about 2kV (IEC61000-4-2).","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122108792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Fayçal, B. Wahiba, B. Lotfi, B. Ratiba, A. Benia
{"title":"Computer Audiometer for Hearing Testing","authors":"Y. Fayçal, B. Wahiba, B. Lotfi, B. Ratiba, A. Benia","doi":"10.1109/ENICS.2008.7","DOIUrl":"https://doi.org/10.1109/ENICS.2008.7","url":null,"abstract":"In this paper, we present a prototype of a simple audiometer CAUM (Computer AUdioMeter) based on a computer equipped with a standard sound card. It is a software developed under windows in order to provide a virtual instrument of a standard audiometer on computer. It has functionality to test a patient's hearing using pure tone testing and white noise masking signal. The functions and performances of the prototype are evaluated by hearing tests and compared with classical AC50 audiometer.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117048150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bluetooth 2.0 Based Wireless Network Testbed Development","authors":"J. Etxaniz, G. Aranguren","doi":"10.1109/ENICS.2008.32","DOIUrl":"https://doi.org/10.1109/ENICS.2008.32","url":null,"abstract":"This paper introduces a real development of a wireless network based on Bluetooth 2.0 technology. This development extends the work of a prior Bluetooth networking implementation. It is an evolution that will be useful for the study of wireless sensor network protocols in the real world, going a step beyond the world of simulators. It will be the testbed where these protocols will be analyzed. Thus, the first step of this process is to measure some metric, as latency, in a first case of topological arrangement. The results for the measures in the prior implementation are included in this paper as well.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Microcoaxial Double Slot Antenna for Interstitial Hyperthermia: Design, Modeling and Validation","authors":"M. Cepeda, A. Vera, L. Leija","doi":"10.1109/ENICS.2008.15","DOIUrl":"https://doi.org/10.1109/ENICS.2008.15","url":null,"abstract":"The effectiveness of hyperthermia is related to the temperature achieved during the therapy, as well as the length time of treatment and tissue characteristics. For the treatment of superficial tumors the radiation is applied through external antennas, while internal tumors are exposed to invasive applicators. To effectively treat deep-stead tumors, these antennas should produce a highly localized specific absorption rate pattern and be efficient radiators at different generator frequencies. In this work a double slot antenna for interstitial hyperthermia in muscle was designed using COMSOL Multiphysicstrade 3.3 and then was evaluated. According to the simulation and test validation, it is possible to increase near to 6 degrees Celsius temperature at a frequency of 2.45 GHz with a power level of 1 Watt.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130616069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Wey, Shin-Yo Lin, Hsu-Sheng Wang, Chun-Ming Huang
{"title":"A Low-Cost Continuous-Flow FFT Processor for UWB Applications","authors":"C. Wey, Shin-Yo Lin, Hsu-Sheng Wang, Chun-Ming Huang","doi":"10.1109/ENICS.2008.20","DOIUrl":"https://doi.org/10.1109/ENICS.2008.20","url":null,"abstract":"In UWB systems, the data symbols are transmitted and received continuously. This study developed a continuous flow parallel memory-based FFT processor (CF-FFT processor) for UWB (ultra wideband) applications. Results show that the developed CF-FFT processor takes approximately 1.31 mm2 to achieve a throughput rate of 1 GS/s, where TSMC0.18 um 1P6M CMOS process was employed.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130864050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"GSM Based Remote Ionized Radiation Monitoring System","authors":"A. Alshamali","doi":"10.1109/ENICS.2008.21","DOIUrl":"https://doi.org/10.1109/ENICS.2008.21","url":null,"abstract":"Nuclear radiation and its effects is a major concern in the world from countries trying to develop the new technology and obsolete reactors that have the potential of leaking dangerous fumes on the health of their entire region. The need for ionized radiation monitoring system to act as an early warning system is essential for the safety of the region. Radiation levels that are not easily noticeable on short term bases might be damaging on long term effects. In this paper, we propose a remote ionized radiation monitoring system using the global system for mobile communication (GSM). Design considerations and implementation of the remote monitoring stations and interconnection to central station via the GSM network are included. The system will continuously measure ionized radiation, store data locally and in case of abnormality (level of radiation becomes greater than the preprogrammed alarm points) alarm messages will be automatically transmitted to the central station.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130402406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Reconfigurable Platform to Drive High Frequency Class S Power Amplifiers Using Multi-gigabit Transceivers","authors":"A. Astarloa, J. Dooley, A. Canniff, R. Farrell","doi":"10.1109/ENICS.2008.13","DOIUrl":"https://doi.org/10.1109/ENICS.2008.13","url":null,"abstract":"In this research work we present a reconfigurable platform that implements all the digital processing and RF carrier generation for the class S power amplifier proposed by the Institute of Microelectronics and Wireless Systems. This amplifier is a combination of a lowpass or bandpass sigma-delta modulation stage in series with a frequency shifting stage and a switch mode amplifier followed by a band pass filter. The reconfigurable platform is parameterizable, scalable and it has been optimized for reconfigurable devices. It takes advantage from the multi-gigabit serial links embedded into the new FPGAs to synthesize binary RF signals, and from the parameterizable soft cores that the FPGA vendor provides. The implementation results for a stand-alone and for a tiny Wishbone compatible system-on-programmable-chip versions are presented. The design is validated with data measured in the simulation and in the prototype.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"358 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113987031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}