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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)最新文献

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Multi-grained reconfigurable datapath structures for online-adaptive reconfigurable hardware architectures 用于在线自适应可重构硬件体系结构的多粒度可重构数据路径结构
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.51
Alexander Thomas, J. Becker
{"title":"Multi-grained reconfigurable datapath structures for online-adaptive reconfigurable hardware architectures","authors":"Alexander Thomas, J. Becker","doi":"10.1109/ISVLSI.2005.51","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.51","url":null,"abstract":"Modern application scenarios out of multimedia and mobile communication domains demand more and more performant data processing architectures, which cannot be achieved by using current DSP or microprocessor approaches. This paper describes a new multi-grained architecture approach out of the reconfigurable array field which offers a set of new features to increase the flexibility and usability of reconfigurable array architectures by increasing the performance benefit concurrently and decreasing the management effort caused by the system controller. Multi-grained support allows execution of multi-grained application as well as realization of flexible control mechanisms for control-based applications. The main focus of this publication is the introduction of the developed datapath structure where the authors discuss the concepts and features in detail.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"6 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132323194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Let's think analog 让我们考虑一下模拟
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.48
M. Breuer
{"title":"Let's think analog","authors":"M. Breuer","doi":"10.1109/ISVLSI.2005.48","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.48","url":null,"abstract":"In the area of testing ICs, once an IC has failed a traditional go/no-go test, it needs to be tested further to determine if it can support error-tolerant operation for one or more high volume customers. This test must be very efficient since many chips will probably fail, and those that pass will be sold at a discount. We have already developed several efficient test procedures to support error-tolerance. One is a built-in self-test methodology that can sort chips into various bins based on their error-rate, just like resistors are sorted into 1%, 5% and 10% bins (Breuer, 2004). Digital systems designers have almost always focused on the concept of exact computational capability. Error-tolerant VLSI chips are a step in this direction using today's technologies, addressing current computational needs, and accepting present realities of scale and yield.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121162065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
A flexible and efficient hardware architecture for real-time face recognition based on eigenface 一种灵活高效的基于特征脸的实时人脸识别硬件架构
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.5
H. T. Ngo, Rajkiran Gottumukkal, V. Asari
{"title":"A flexible and efficient hardware architecture for real-time face recognition based on eigenface","authors":"H. T. Ngo, Rajkiran Gottumukkal, V. Asari","doi":"10.1109/ISVLSI.2005.5","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.5","url":null,"abstract":"We describe a flexible and efficient multilane architecture for real-time face recognition system based on modular principal component analysis (PCA) method in a field programmable gate array (FPGA) environment. We have shown in Gottumukkal R., and Asan K.V., (2004) that modular PCA improves the accuracy of face recognition when the face images have varying expression and illumination. The flexible and parallel architecture design consists of multiple processing elements to operate on predefined regions of a face image. Each processing element is also parallelized with multiple pipelined paths/lanes to simultaneously compute weight vectors of the non-overlapping region, hence called multilane architecture. The architecture is able to recognize a face image from a database of 1000 face images in 11ms.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114155246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Synthesis of self-resetting stage logic pipelines 自复位级逻辑管道的合成
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.70
A. Alsharqawi, A. Ejnioui
{"title":"Synthesis of self-resetting stage logic pipelines","authors":"A. Alsharqawi, A. Ejnioui","doi":"10.1109/ISVLSI.2005.70","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.70","url":null,"abstract":"In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an integer programming (IP) problem subject to area and timing constraints for which an exact procedure is proposed. Currently, the proposed solution is being implemented and tested on a set of benchmark circuits. Also, fast heuristics are being developed to synthesize large gate netlists into SRSL pipelines.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130117844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and implementation of FPGA router for efficient utilization of heterogeneous routing resources FPGA路由器的设计与实现，有效利用异构路由资源
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.26
Deepak Rautela, R. Katti
{"title":"Design and implementation of FPGA router for efficient utilization of heterogeneous routing resources","authors":"Deepak Rautela, R. Katti","doi":"10.1109/ISVLSI.2005.26","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.26","url":null,"abstract":"The routing resources available in recent FPGA architectures (e.g., Xilinx Virtex-II) are very different from the older generation of FPGAs (e.g., Xilinx XC4000). The latest FPGA architectures have heterogeneous routing resources which include directly driven wires of different lengths and connectivity. Since routing resources in FPGAs are fixed, it is very important for the routing algorithms to fully exploit the potential of new routing architectures. FPGA routing architectures are usually represented as a routing resource graph (RRG). In this paper we present a simplified scheme to build the RRG for FPGA architectures with heterogeneous routing resources. Using our RRG construction scheme we have built a mutability driven FPGA router named \"Bison\". We also present two dynamic weight update based heuristics which we have incorporated into the router, so that efficient utilization of routing resources can be achieved.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130317793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An improved dynamic optically reconfigurable gate array 一种改进的动态光可重构门阵列
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.16
Minoru Watanabe, F. Kobayashi
{"title":"An improved dynamic optically reconfigurable gate array","authors":"Minoru Watanabe, F. Kobayashi","doi":"10.1109/ISVLSI.2005.16","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.16","url":null,"abstract":"To date, we have proposed dynamic optically reconfigurable gate arrays (DORGAs), the implemented photodiodes of which serve not only as receivers but also as memory. DORGA offers the merit of easily providing a high gate count optically reconfigurable gate array (ORGA) because each reconfiguration circuit consists of only a photodiode and a refresh transistor. However, even though the fast reconfiguration capability has been confirmed as less than 6 ns, such systems have a demerit: their gate arrays can not function during reconfiguration. Consequently, reconfiguration and operation of the implemented circuit on a gate array can not be executed in parallel. Because of that fact, the dynamical reconfiguration frequency of DORGA is slow compared to those of ORGAs with latches, flip-flops, or memory. For that reason, this paper proposes a new optical reconfiguration architecture. Using it, the reconfiguration and implemented circuit operation on a gate array are executable in parallel merely by adding a pass transistor. The new design of a 476-gate-count improved DORGA using a standard 0.35 /spl mu/m three-metal CMOS process technology is also shown.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115262407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RG-SRAM: a low gate leakage memory design RG-SRAM:一种低栅漏存储器设计
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.64
Charan Thondapu, P. Elakkumanan, R. Sridhar
{"title":"RG-SRAM: a low gate leakage memory design","authors":"Charan Thondapu, P. Elakkumanan, R. Sridhar","doi":"10.1109/ISVLSI.2005.64","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.64","url":null,"abstract":"The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel reduced-gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in very deep sub-micron (VDSM) cache and embedded memories.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128287873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Hardware implementation of an additive bit-serial algorithm for the discrete logarithm modulo 2/sup k/ 离散对数模2/sup k/的加性位串行算法的硬件实现
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.35
Lun Li, A. Fit-Florea, M. Thornton, D. Matula
{"title":"Hardware implementation of an additive bit-serial algorithm for the discrete logarithm modulo 2/sup k/","authors":"Lun Li, A. Fit-Florea, M. Thornton, D. Matula","doi":"10.1109/ISVLSI.2005.35","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.35","url":null,"abstract":"We describe the hardware implementation of a novel algorithm for computing the discrete logarithm modulo 2/sup k/. The circuit has a total latency of less than k table-lookup-determined shift-and-add modulo 2/sup k/ operations. We introduce a one-to-one mapping between k-bit binary integers and k-bit encodings of a factorization of the integers employing the discrete logarithm. We compare the physical layout result for the circuit when k = 8, 16, 32, and 64.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1938 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128801475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reduction of power and test time by removing cluster of don't-care from test data set 通过从测试数据集中去除不关心的簇来减少功率和测试时间
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.63
Il-soo Lee, Yu-Ting Lin, A. Ambler
{"title":"Reduction of power and test time by removing cluster of don't-care from test data set","authors":"Il-soo Lee, Yu-Ting Lin, A. Ambler","doi":"10.1109/ISVLSI.2005.63","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.63","url":null,"abstract":"Reduction of power dissipation and test time is accomplished by forming two clusters of don't-care inside an input and a response test cube, respectively. These clusters are out of the scan operation.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130890767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a QCA memory with parallel read/serial write 具有并行读/串行写功能的QCA存储器的设计
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.27
M. Ottavi, V. Vankamamidi, F. Lombardi, S. Pontarelli, A. Salsano
{"title":"Design of a QCA memory with parallel read/serial write","authors":"M. Ottavi, V. Vankamamidi, F. Lombardi, S. Pontarelli, A. Salsano","doi":"10.1109/ISVLSI.2005.27","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.27","url":null,"abstract":"This paper presents a novel memory architecture for implementation by quantum-dot cellular automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122972186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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