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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)最新文献

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Pipelined memory controllers for DSP applications handling unpredictable data accesses 流水线存储器控制器的DSP应用程序处理不可预测的数据访问
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.56
B. Gal, E. Casseau, Sylvain Huet, E. Martin
{"title":"Pipelined memory controllers for DSP applications handling unpredictable data accesses","authors":"B. Gal, E. Casseau, Sylvain Huet, E. Martin","doi":"10.1109/ISVLSI.2005.56","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.56","url":null,"abstract":"Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access controllers can be generated improving the pipeline access mode to RAM. We focus on the design and the implementation of memory sequencers that can be automatically generated from a behavioral synthesis tool and which can efficiently handle predictable address patterns as well as unpredictable ones (dynamic address computations) in a pipeline way.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126560753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Evaluating the data integrity of memory systems by configurable Markov models 用可配置马尔可夫模型评价存储系统的数据完整性
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.30
M. Ottavi, L. Schiano, F. Lombardi, S. Pontarelli, G. Cardarilli
{"title":"Evaluating the data integrity of memory systems by configurable Markov models","authors":"M. Ottavi, L. Schiano, F. Lombardi, S. Pontarelli, G. Cardarilli","doi":"10.1109/ISVLSI.2005.30","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.30","url":null,"abstract":"In this paper, a novel method for the evaluation of the bit error rate (BER) as measure for assessing data integrity in memory systems is proposed; such method improves modeling by introducing configurability features in the Markov chains to account for environmental and operational changes. For modeling erasures and random errors, the occurrence of new time-varying features is introduced in the analysis to characterize the behavior of memory systems for space applications (using Reed-Solomon codes as EDAC). Moreover, differently from existing techniques, the nature of these features (such as scrubbing and the effects of the so-called South Atlantic Anomaly on SEU rates) is assessed using a deterministic framework.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126088758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power analysis of rotary clock 旋转时钟的功率分析
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.58
Zhengtao Yu, Xun Liu
{"title":"Power analysis of rotary clock","authors":"Zhengtao Yu, Xun Liu","doi":"10.1109/ISVLSI.2005.58","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.58","url":null,"abstract":"Rotary clock is a multi-gigahertz clock distribution technique based on the principle of wave propagation in transmission lines. In this paper, we perform the first quantitative investigation on the power dissipation of rotary clock designs. Specifically, we have developed a software tool based on the method of partial element equivalent circuit (PEEC) that is capable of extracting the SPICE netlist from a layout specification of a rotary clock design. As a result, we are able to accurately estimate the frequency and power dissipation of the rotary clock design using SPICE simulations. Using our tool, we have uncovered the key power dissipation mechanisms of rotary clock and proposed several power reduction strategies. Furthermore, our power analysis has revealed that rotary clock designs can achieve power savings of up to 70% in comparison with conventional clock tree implementations.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"626 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133107877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Wire length distribution model considering core utilization for system on chip 考虑芯利用率的片上系统导线长度分布模型
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.76
T. Kyogoku, J. Inoue, H. Nakashima, T. Uezono, K. Okada, K. Masu
{"title":"Wire length distribution model considering core utilization for system on chip","authors":"T. Kyogoku, J. Inoue, H. Nakashima, T. Uezono, K. Okada, K. Masu","doi":"10.1109/ISVLSI.2005.76","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.76","url":null,"abstract":"This paper presents a new model to estimate wire length distribution (WLD) of system on chip (SoC). The WLD represents a correlation between wire length and the number of interconnect, and we can predict power consumption, maximum clock frequency, chip size, etc with the WLD. The proposed model provides a WLD considering each core utilization of several macro blocks in a system LSI. We present an optimization method to determine each core utilization.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133979169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The use of pre-evaluation phase in dynamic CMOS logic 预估相位在动态CMOS逻辑中的应用
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.72
A. Rao, T. Haniotakis, Y. Tsiatouhas, H. Djemil
{"title":"The use of pre-evaluation phase in dynamic CMOS logic","authors":"A. Rao, T. Haniotakis, Y. Tsiatouhas, H. Djemil","doi":"10.1109/ISVLSI.2005.72","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.72","url":null,"abstract":"Dynamic logic families have been shown to offer performance advantages over traditional CMOS logic. Their operation is based on the use of a clock signal that provides two operation phases: the precharge phase and evaluation phase. The precharge phase is setting the circuit at a predefined initial state while the actual logic response is determined during the evaluation phase. In this paper we examine potential advantages when an additional phase, called pre-evaluation, is introduced. During this phase a restricted voltage swing occurs depending on the desired outcome. This voltage swing is amplified during the final evaluation in order to produce the final logic response. By restricting the required voltage swing at internal logic nodes (especially in case of those presenting high capacitance) we are able to achieve higher performance coupled with reduced power consumption.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131003153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Leakage power driven behavioral synthesis of pipelined datapaths 泄漏功率驱动的流水数据路径行为综合
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.46
R. Gopalan, C. Gopalakrishnan, S. Katkoori
{"title":"Leakage power driven behavioral synthesis of pipelined datapaths","authors":"R. Gopalan, C. Gopalakrishnan, S. Katkoori","doi":"10.1109/ISVLSI.2005.46","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.46","url":null,"abstract":"We present a scheduling, allocation and binding methodology that employs MTCMOS as the standby leakage reduction mechanism. We use the simulated annealing meta-heuristic for optimizing leakage power The cost functions for our approach are obtained after extensive characterization trials taking into account, the run-time characteristics of the MTCMOS approach. Our approach makes use of two cost factors: leakage cost, for optimizing the number of MTCMOS instances, and settling cost, for the minimization of their active-to-standby transitions. We enhance throughput and performance of the datapaths by synthesizing them as functionally pipelined systems before performing our optimizations. Using fully pre-characterized leakage libraries for RT-level simulation, we obtain an average leakage power reduction of 36.2%, and an average area overhead of 6.2%. However, with a small increase in schedule latency, we obtain an average reduction of around 3.95%-4.6% in the total area.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131422777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reduction of direct tunneling power dissipation during behavioral synthesis of nanometer CMOS circuits 纳米CMOS电路行为合成过程中直接隧穿功耗的降低
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.62
S. Mohanty, R. Velagapudi, V. Mukherjee, Hao Li
{"title":"Reduction of direct tunneling power dissipation during behavioral synthesis of nanometer CMOS circuits","authors":"S. Mohanty, R. Velagapudi, V. Mukherjee, Hao Li","doi":"10.1109/ISVLSI.2005.62","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.62","url":null,"abstract":"Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO/sub 2/) is very low. We intuitively believe that multiple oxide thickness may be useful to reduce the direct tunneling current dissipation. Since no foundry design rules are available for design and layout using technology below 90nm we provide analytical models to calculate the tunneling current and the propagation delay of behavioral level components. We then characterize those components for 45nm technology and provide an algorithm for scheduling of datapath operations such that the overall tunneling power dissipation of the circuit is minimal. We have carried out extensive experiments for various behavioral level benchmarks under various constraints and observed significant reductions.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117354679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of a mask-based nanowire decoder 基于掩模的纳米线解码器分析
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.17
Eric Rachlin, J. Savage, Benjamin Gojman
{"title":"Analysis of a mask-based nanowire decoder","authors":"Eric Rachlin, J. Savage, Benjamin Gojman","doi":"10.1109/ISVLSI.2005.17","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.17","url":null,"abstract":"A key challenge facing nanotechnologies will be controlling nanoarrays, two orthogonal sets of nanowires that form a crossbar, using a moderate number of mesoscale wires. Three methods have been proposed to use mesoscale wires to control individual nanowires. The first is based on nanowire differentiation during manufacture, the second makes random doped connections between nanowires and mesoscale wires, and the third, a mask-based approach, interposes high-K dielectric regions between nanowires and mesoscale wires. All three addressing schemes involve a stochastic step in their implementation. In this paper, we analyze the mask-based approach and show that a large number of mesoscale control wires is necessary for its realization.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125504377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Quasi-exact BDD minimization using relaxed best-first search 使用松弛最佳优先搜索的准精确BDD最小化
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI: 10.1109/ISVLSI.2005.59
Rüdiger Ebendt, R. Drechsler
{"title":"Quasi-exact BDD minimization using relaxed best-first search","authors":"Rüdiger Ebendt, R. Drechsler","doi":"10.1109/ISVLSI.2005.59","DOIUrl":"https://doi.org/10.1109/ISVLSI.2005.59","url":null,"abstract":"In this paper, we present a new method for quasi-exact optimization of BDDs using relaxed ordered best-first search. This general method is applied to BDD minimization. In contrast to a known relaxation of A*, the new method guarantees to expand every state exactly once if guided by a monotone heuristic function. By that, it effectively accounts for aspects of run time while still guaranteeing that the cost of the solution does not exceed the optimal cost by a factor greater than (1 + /spl epsi/)/sup /spl lfloor/n/2/spl rfloor// where n is the maximal length of a solution path. E.g., for 25 BDD variables and using a degree of relaxation of 5%, the BDD size is guaranteed to be not greater than 1.8 times the optimal size. Within a range of reasonable choices for /spl epsi/, the method allows the user to trade off run time for solution quality. Experimental results demonstrate large reductions in run time when compared to the best known exact approach. Moreover, the quality of the obtained solutions is much better than the quality guaranteed by the theory.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115037653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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