考虑芯利用率的片上系统导线长度分布模型

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI:10.1109/ISVLSI.2005.76

T. Kyogoku, J. Inoue, H. Nakashima, T. Uezono, K. Okada, K. Masu

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引用次数: 3

摘要

提出了一种估计片上系统(SoC)导线长度分布(WLD)的新模型。WLD表示线长和互连数之间的相关性，我们可以用WLD预测功耗、最大时钟频率、芯片尺寸等。提出的模型提供了一个考虑系统LSI中几个宏块的每个核心利用率的WLD。我们提出了一种优化方法来确定每个核心的利用率。

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Wire length distribution model considering core utilization for system on chip

This paper presents a new model to estimate wire length distribution (WLD) of system on chip (SoC). The WLD represents a correlation between wire length and the number of interconnect, and we can predict power consumption, maximum clock frequency, chip size, etc with the WLD. The proposed model provides a WLD considering each core utilization of several macro blocks in a system LSI. We present an optimization method to determine each core utilization.

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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