RG-SRAM: a low gate leakage memory design

Abstract

The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel reduced-gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in very deep sub-micron (VDSM) cache and embedded memories.