离散对数模2/sup k/的加性位串行算法的硬件实现

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI:10.1109/ISVLSI.2005.35

Lun Li, A. Fit-Florea, M. Thornton, D. Matula

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引用次数: 6

摘要

我们描述了一种计算离散对数模2/sup k/的新算法的硬件实现。电路的总延迟小于k次表查找决定的移位加模2/sup k/次操作。我们引入了k位二进制整数和k位编码之间的一对一映射，这些整数采用离散对数分解。我们比较了k = 8,16,32和64时电路的物理布局结果。

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Hardware implementation of an additive bit-serial algorithm for the discrete logarithm modulo 2/sup k/

We describe the hardware implementation of a novel algorithm for computing the discrete logarithm modulo 2/sup k/. The circuit has a total latency of less than k table-lookup-determined shift-and-add modulo 2/sup k/ operations. We introduce a one-to-one mapping between k-bit binary integers and k-bit encodings of a factorization of the integers employing the discrete logarithm. We compare the physical layout result for the circuit when k = 8, 16, 32, and 64.

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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