RG-SRAM:一种低栅漏存储器设计

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI:10.1109/ISVLSI.2005.64

Charan Thondapu, P. Elakkumanan, R. Sridhar

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引用次数: 5

摘要

在sub-70nm制程技术中，栅极氧化物厚度接近于直接栅极隧道电流开始在开关态晶体管中发挥重要作用的极限。在本文中，我们提出了一种新型的减少栅极SRAM (RG-SRAM)，它使用两个额外的PMOS通路晶体管来降低极深亚微米(VDSM)高速缓存和嵌入式存储器中的栅极泄漏损耗。

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RG-SRAM: a low gate leakage memory design

The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel reduced-gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in very deep sub-micron (VDSM) cache and embedded memories.

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来源期刊

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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