Hardware implementation of an additive bit-serial algorithm for the discrete logarithm modulo 2/sup k/

Abstract

We describe the hardware implementation of a novel algorithm for computing the discrete logarithm modulo 2/sup k/. The circuit has a total latency of less than k table-lookup-determined shift-and-add modulo 2/sup k/ operations. We introduce a one-to-one mapping between k-bit binary integers and k-bit encodings of a factorization of the integers employing the discrete logarithm. We compare the physical layout result for the circuit when k = 8, 16, 32, and 64.