Synthesis of self-resetting stage logic pipelines

Abstract

In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an integer programming (IP) problem subject to area and timing constraints for which an exact procedure is proposed. Currently, the proposed solution is being implemented and tested on a set of benchmark circuits. Also, fast heuristics are being developed to synthesize large gate netlists into SRSL pipelines.