自复位级逻辑管道的合成

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI:10.1109/ISVLSI.2005.70

A. Alsharqawi, A. Ejnioui

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引用次数: 2

摘要

本文提出了一种合成SRSL管道的方法。将SRSL管道的综合表述为一个受面积和时间约束的整数规划问题，并给出了具体的求解过程。目前，提出的解决方案正在一组基准电路上实施和测试。此外，正在开发快速启发式方法，将大型门网合成为SRSL管道。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Synthesis of self-resetting stage logic pipelines

In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an integer programming (IP) problem subject to area and timing constraints for which an exact procedure is proposed. Currently, the proposed solution is being implemented and tested on a set of benchmark circuits. Also, fast heuristics are being developed to synthesize large gate netlists into SRSL pipelines.

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来源期刊

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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