2010 IEEE International Memory Workshop最新文献

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Impact of plasma gate reoxidation on the non-volatile charge trap memory device 等离子栅再氧化对非易失性电荷阱存储器件的影响
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488408
D. Gilmer, K. Lim, H. Park, C. Park, N. Goel, P. Kirsch, R. Jammy
{"title":"Impact of plasma gate reoxidation on the non-volatile charge trap memory device","authors":"D. Gilmer, K. Lim, H. Park, C. Park, N. Goel, P. Kirsch, R. Jammy","doi":"10.1109/IMW.2010.5488408","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488408","url":null,"abstract":"Post gate-etch reoxidation in plasma H2/O2 was successfully employed to non-volatile TANOS charge-trap memory devices without any adverse oxidation on the TaN gate-electrode sidewall. Using this plasma reoxidation process showed significant device improvement in the narrow gate retention and endurance characteristics. This improvement is thought to result from gate etch damage repair, and locally thicker tunnel oxide formation near the gate edge, from the plasma reoxidation process. Circumventing gate etch damage will be indispensable for sub-30nm charge-trap flash memory devices.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121176711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On Carbon doping to improve GeTe-based Phase-Change Memory data retention at high temperature 碳掺杂提高gete相变存储器高温数据保留性能的研究
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488328
G. Beneventi, E. Gourvest, Andrea Fantini, L. Perniola, V. Sousa, S. Maitrejean, J. Bastien, A. Bastard, A. Fargeix, B. Hyot, C. Jahan, J. Nodin, A. Persico, D. Blachier, A. Toffoli, S. Loubriat, A. Roule, Sandrine Lhostis, H. Feldis, G. Reimbold, T. Billon, B. D. Salvo, Luca Larcher, Paolo Pavan, Daniel Bensahel, Pascale Mazoyer, R. Annunziata, F. Boulanger
{"title":"On Carbon doping to improve GeTe-based Phase-Change Memory data retention at high temperature","authors":"G. Beneventi, E. Gourvest, Andrea Fantini, L. Perniola, V. Sousa, S. Maitrejean, J. Bastien, A. Bastard, A. Fargeix, B. Hyot, C. Jahan, J. Nodin, A. Persico, D. Blachier, A. Toffoli, S. Loubriat, A. Roule, Sandrine Lhostis, H. Feldis, G. Reimbold, T. Billon, B. D. Salvo, Luca Larcher, Paolo Pavan, Daniel Bensahel, Pascale Mazoyer, R. Annunziata, F. Boulanger","doi":"10.1109/IMW.2010.5488328","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488328","url":null,"abstract":"This paper investigates material and electrical properties of a new chalcogenide alloy for Phase-Change Memories (PCM): Carbon-doped GeTe (named GeTeC). First, several physico-chemical, optical and electrical analyses have been performed on full-sheet chalcogenide depositions in order to understand the intrinsic GeTeC phase-change behavior, and to characterize structure and composition of amorphous and crystalline states. Then, GeTeC with two different Carbon doping (4% and 10%) has been integrated in pillar-type analytical PCM cells. Physico-chemical and electrical data indicate that GeTeC is characterized by a much more stable amorphous phase compared to undoped GeTe. Thus, GeTeC offers a slower programming speed versus GeTe, but an improved data retention at high temperature. Finally, we argue that GeTeC alloy is a promising candidate for future developments of PCM technologies for embedded applications.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126744412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Zero-cost MTP high density NVM modules in a CMOS process flow CMOS工艺流程中的零成本MTP高密度NVM模块
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488313
A. Atrash, G. Cassuto, W. Chen, V. Dayan, O. Galzur, M. Gutman, A. Heiman, G. Hunsinger, D. Nahmad, A. Parag, E. Pikhay, Y. Roizin, B. Smith, A. Strum, T. Tishbi, R. Teggatz
{"title":"Zero-cost MTP high density NVM modules in a CMOS process flow","authors":"A. Atrash, G. Cassuto, W. Chen, V. Dayan, O. Galzur, M. Gutman, A. Heiman, G. Hunsinger, D. Nahmad, A. Parag, E. Pikhay, Y. Roizin, B. Smith, A. Strum, T. Tishbi, R. Teggatz","doi":"10.1109/IMW.2010.5488313","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488313","url":null,"abstract":"A zero-cost embedded high density MTP NVM with extensive statistical verification is presented. The family of compact single Poly modules ranging from 64bit to 64kbit is based on the Y-Flash concept, employing original array architectures and implemented in standard and power management (PM) 0.18um CMOS process flows. No special HV devices or additional masks are employed. Excellent reliability performance allowing more than 10k program/erase cycles and 10year data retention at 150°C is demonstrated.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121535722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Comparative study of non-polar switching behaviors of NiO- and HfO2-based Oxide Resistive-RAMs NiO-和hfo2基氧化物阻性ram非极性开关行为的比较研究
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488316
V. Jousseaume, A. Fantini, J. Nodin, C. Guedj, A. Persico, J. Buckley, S. Tirano, P. Lorenzi, R. Vignon, H. Feldis, S. Minoret, H. Grampeix, A. Roule, S. Favier, E. Martinez, P. Calka, N. Rochat, G. Auvert, J. Barnes, P. Gonon, C. Vallée, L. Perniola, B. De Salvo
{"title":"Comparative study of non-polar switching behaviors of NiO- and HfO2-based Oxide Resistive-RAMs","authors":"V. Jousseaume, A. Fantini, J. Nodin, C. Guedj, A. Persico, J. Buckley, S. Tirano, P. Lorenzi, R. Vignon, H. Feldis, S. Minoret, H. Grampeix, A. Roule, S. Favier, E. Martinez, P. Calka, N. Rochat, G. Auvert, J. Barnes, P. Gonon, C. Vallée, L. Perniola, B. De Salvo","doi":"10.1109/IMW.2010.5488316","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488316","url":null,"abstract":"This paper presents a detailed comparative study of the switching characteristics of resistive memory devices, with NiO or HfO2 active materials and Pt electrodes, based on identical integration schemes. Material screening and qualification are performed using structural and composition analyses. Preliminary electrical investigations outline the non-polar switching behavior of both HfO2 and NiO devices. Then, by using a specific test setup, we present a systematic comparative study of HfO2 and NiO devices, clearly showing the tunability of the electrical characteristics with material type and process. HfO2 devices lead to largest High Resistance State/Low Resistance State ratios and higher forming voltages compared to NiO cells, while reset voltages are similar. Data retention of both materials show highly stable Low Resistance State state, while High Resistance State increases over time under 85°C baking.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"15 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131573163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Non-volatile memories in the foundry business 非易失性存储器在铸造业务
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488394
A. Strum, Todd Mahlen, Y. Roizin
{"title":"Non-volatile memories in the foundry business","authors":"A. Strum, Todd Mahlen, Y. Roizin","doi":"10.1109/IMW.2010.5488394","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488394","url":null,"abstract":"The role of non-volatile memory (NVM) technologies in the business of silicon foundries is reviewed. Solutions that comply with the NVM requests of diverse customers in today's semiconductor market are analyzed both from technical and business viewpoints. The strategy of NVM internal development in a foundry, the availability of NVM for special technology platforms, and the compromise between internal and external memory intellectual property (IP) are discussed using TowerJazz memory solutions as examples.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121127166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Scalability enhancement of FG NAND by FG shape modification 通过FG形状修饰提高FG NAND的可扩展性
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488389
U. Ganguly, Y. Yokota, Jing Tang, Shiyu Sun, Matt Rogers, M. Jin, K. Thadani, H. Hamana, G. Leung, Balaji Chandrasekaran, S. Thirupapuliyur, C. Olsen, Vicky Nguyen, S. Srinivasan
{"title":"Scalability enhancement of FG NAND by FG shape modification","authors":"U. Ganguly, Y. Yokota, Jing Tang, Shiyu Sun, Matt Rogers, M. Jin, K. Thadani, H. Hamana, G. Leung, Balaji Chandrasekaran, S. Thirupapuliyur, C. Olsen, Vicky Nguyen, S. Srinivasan","doi":"10.1109/IMW.2010.5488389","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488389","url":null,"abstract":"Floating Gate (FG) NAND scaling has been severely challenged by the reduction of gate coupling ratio (CR) and increase in FG interference (FGI) below 30nm node. Firstly, scalability of inverted ‘T’ shaped FG is evaluated by 3D electrostatics simulation. It is shown that coupling ratio (CR) and Floating Gate Interference (FGI) performance can be maintained at the level of 34nm technology down to 13nm node by engineering key aspects of the FG shape namely FG top width (FGW) and effective field height (EFH) in addition to conventional scaling approaches of IPD thinning and spacer к reduction. Secondly, FG shaping is demonstrated down to FGW of 3nm and EFH of 5nm using a sacrificial oxidation technology with no bird's beak to demonstrate fabrication feasibility.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"348 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133287205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Through-silicon-via technology for 3D integration 通过硅通孔技术进行3D集成
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488399
J. Dukovic, S. Ramaswami, S. Pamarthy, R. Yalamanchili, N. Rajagopalan, K. Sapre, Z. Cao, T. Ritzdorf, Y. Wang, B. Eaton, R. Ding, M. Hernandez, M. Naik, D. Mao, J. Tseng, D. Cui, G. Mori, P. Fulmer, K. Sirajuddin, J. Hua, S. Xia, D. Erickson, R. Beica, E. Young, P. Kusler, R. Kulzer, S. Oemardani, H. Dai, X. Xu, M. Okazaki, K. Dotan, C. Yu, C. Lazik, J. Tran, L. Luo
{"title":"Through-silicon-via technology for 3D integration","authors":"J. Dukovic, S. Ramaswami, S. Pamarthy, R. Yalamanchili, N. Rajagopalan, K. Sapre, Z. Cao, T. Ritzdorf, Y. Wang, B. Eaton, R. Ding, M. Hernandez, M. Naik, D. Mao, J. Tseng, D. Cui, G. Mori, P. Fulmer, K. Sirajuddin, J. Hua, S. Xia, D. Erickson, R. Beica, E. Young, P. Kusler, R. Kulzer, S. Oemardani, H. Dai, X. Xu, M. Okazaki, K. Dotan, C. Yu, C. Lazik, J. Tran, L. Luo","doi":"10.1109/IMW.2010.5488399","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488399","url":null,"abstract":"Major efforts are currently underway throughout the IC industry to develop the capability to integrate device chips by stacking them vertically and using through-silicon vias (TSVs). The resulting interconnect density, bandwidth, and compactness achievable by TSV technology exceed what is currently possible by other packaging approaches. Market-driven applications of TSV involving memory include multi-chip high-performance DRAM, integration of memory and logic functions for enhanced video on handheld devices, and stacked NAND flash for solid-state drives. High-volume commercial implementation of 3D TSV is imminent but faced by special challenges of design, fabrication, bonding, test, reliability, know-good die, standards, logistics, and overall cost. The main focus of this paper is the unit-process and process-integration technology required for TSV fabrication at the wafer level: deep silicon etching, dielectric via isolation, metallization, metal fill, and chemical-mechanical polishing.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132206827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Design impacts on NAND Flash memory core circuits with vertical MOSFETs 垂直mosfet对NAND闪存磁芯电路设计的影响
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488310
K. Sakui, T. Endoh
{"title":"Design impacts on NAND Flash memory core circuits with vertical MOSFETs","authors":"K. Sakui, T. Endoh","doi":"10.1109/IMW.2010.5488310","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488310","url":null,"abstract":"By utilizing the vertical MOSFETs advantages, the compact, efficient, and low-power peripheral core circuit design for the NAND Flash memory has been proposed.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128216716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CuxO-based resistive memory with low power and high reliability for SOC nonvolatile memory applications 一种基于cuxo的电阻式存储器,具有低功耗和高可靠性,适用于SOC非易失性存储器应用
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488318
M. Wang, Y. L. Song, H. Wan, H. Lv, P. Zhou, T. Tang, Y. Y. Lin, R. Huang, S. Song, J. Wu, H. Wu, M. Chi
{"title":"A CuxO-based resistive memory with low power and high reliability for SOC nonvolatile memory applications","authors":"M. Wang, Y. L. Song, H. Wan, H. Lv, P. Zhou, T. Tang, Y. Y. Lin, R. Huang, S. Song, J. Wu, H. Wu, M. Chi","doi":"10.1109/IMW.2010.5488318","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488318","url":null,"abstract":"A CuxO-based resistive memory is successfully integrated in 0.13µm logic process. Operation algorithm is optimized to achieve low power consumption with reset current down to 30 µA. High thermal stability and small cell size less than 22F2 have been demonstrated. The advantages make this device promising for system on chip non-volatile memory applications.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134304178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of material composition on the write performance of phase-change memory devices 材料成分对相变存储器件写入性能的影响
2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488329
M. Boniardi, D. Ielmini, A. Lacaita, A. Redaelli, A. Pirovano, I. Tortorelli, M. Allegra, M. Magistretti, C. Bresolin, D. Erbetta, A. Modelli, E. Varesi, F. Pellizzer, R. Bez
{"title":"Impact of material composition on the write performance of phase-change memory devices","authors":"M. Boniardi, D. Ielmini, A. Lacaita, A. Redaelli, A. Pirovano, I. Tortorelli, M. Allegra, M. Magistretti, C. Bresolin, D. Erbetta, A. Modelli, E. Varesi, F. Pellizzer, R. Bez","doi":"10.1109/IMW.2010.5488329","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488329","url":null,"abstract":"The phase-change memory (PCM) technology represents one of the most attractive concepts for next generation data storage. PCM operation is based on the particular properties of a chalcogenide alloy, the ternary compound Ge2Sb2Te5, which is able to perform fast and reversible transitions between a crystalline, high-conductive phase and an amorphous, low-conductive one, thus enabling the binary data storage. Although the ternary alloy Ge2Sb2Te5 is the best recognised solution to meet the device reliability and performance specifications, other alloys are being studied within the GeSbT e ternary compound system in order to investigate and to enlarge the possible spectrum of PCM applications. This work focuses both on the program parameters and on the write performances of a Sb-rich GST composition, suggesting a change in the physical properties of the PCM material and a transition from nucleation to growth-dominated crystallization mechanism, both controlled by the material composition engineering. This enables new challenging performance parameters.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124672503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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