2010 IEEE International Memory Workshop最新文献_第6页

Highly-scalable disruptive reading scheme for Gb-scale SPRAM and beyond 用于gb级SPRAM及以上的高度可扩展的破坏性读取方案

2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488324

R. Takemura, T. Kawahara, K. Ono, K. Miura, H. Matsuoka, H. Ohno

引用次数: 52

Charge loss in TANOS devices caused by Vt sensing measurements during retention 在保留期间由Vt传感测量引起的TANOS器件中的电荷损失

2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488409

H. Park, G. Bersuker, D. Gilmer, K. Lim, M. Jo, H. Hwang, A. Padovani, L. Larcher, P. Pavan, W. Taylor, P. Kirsch

引用次数: 10

Study of electron and hole injection statistics of BE-SONOS NAND Flash BE-SONOS NAND闪存的电子和空穴注入统计研究

2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488308

H. Lue, T. Hsu, S. Lai, Yan-Ru Chen, Kuan-Fu Chen, C. Lo, I. Huang, T. Han, M. Chen, W. P. Lu, K. C. Chen, Chih-Shen Chang, M. Liaw, K. Hsieh, Chih-Yuan Lu

引用次数: 7

Highly-reliable NAND flash memory using Al2O3-inserted inter-poly dielectric 高可靠的NAND快闪记忆体，使用al2o3插入的聚间介电体

2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488413

Sung-Hae Lee, B. Koo, K. Hwang, Siyoung Choi, J. Moon

引用次数: 0

Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs 制造后，17倍可接受的原始误码率提高，动态码字转换ECC方案，高可靠的固态硬盘，ssd

2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488311

S. Tanakamaru, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, K. Takeuchi

{"title":"Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs","authors":"S. Tanakamaru, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, K. Takeuchi","doi":"10.1109/IMW.2010.5488311","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488311","url":null,"abstract":"A dynamic codeword transition ECC scheme is proposed for highly reliable solid-state drives, SSDs. By monitoring the error number or the write / erase cycles, the ECC codeword dynamically increases from 512Byte (+parity) to 1KByte, 2KByte, 4KByte…32KByte. The proposed ECC with a larger codeword decreases the failure rate after ECC. As a result, the acceptable raw bit error rate, BER, before ECC is enhanced. Assuming a NAND Flash memory which requires 8-bit correction in 512Byte codeword ECC, a 17-times higher acceptable raw BER than the conventional fixed 512Byte codeword ECC is realized for the mobile phone application without an interleaving. For the MP3 player, digital-still camera and high-speed memory card applications with a dual channel interleaving, 15-times higher acceptable raw BER is achieved. Finally, for the SSD application with 8 channel interleaving, 13-times higher acceptable raw BER is realized. Because the parity rate per codeword is the same in each ECC codeword, no additional memory area is required. Note that the reliability of SSD is improved after the manufacturing without cost penalty. Compared with the conventional ECC with the fixed large 32KByte codeword, the proposed scheme achieves a better performance and a lower power consumption by introducing the “best-effort” type operation. In the proposed scheme, during the most of the lifetime of SSD, a weak ECC with a shorter codeword such as 512Byte (+parity), 1KByte and 2KByte is used and a 2.6 times better performance and a 98% lower power consumption is realized. At the life-end of SSD, a strong ECC with a 32KByte codeword is used and the highly reliable operation is achieved.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126975075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

A comparative study of the program efficiency of gate all around SONOS and TANOS flash memory 围绕SONOS和TANOS闪存的栅极程序效率的比较研究

2010 IEEE International Memory Workshop Pub Date : 2010-05-16 DOI: 10.1109/IMW.2010.5488407

Junghwan Ji, Byung-Gook Park, Jong Ho Lee, Hyungcheol Shin

引用次数: 1

General chair 一般的椅子

2010 IEEE International Memory Workshop Pub Date : 1900-01-01 DOI: 10.1109/pdgc.2014.7030702

E. Joelianto, Wahidin Wahab, A. Widyotriatmo, Kuntoro Priyambodo, Sreenatha Gopalarao, Diah Chaerani, Estiko Riyanto, Indah E. Wijayanti, Mohd. Rizal, K. Hamzah., Ling Keck, Rajmohan Madhavan

引用次数: 0