A. Atrash, G. Cassuto, W. Chen, V. Dayan, O. Galzur, M. Gutman, A. Heiman, G. Hunsinger, D. Nahmad, A. Parag, E. Pikhay, Y. Roizin, B. Smith, A. Strum, T. Tishbi, R. Teggatz
{"title":"CMOS工艺流程中的零成本MTP高密度NVM模块","authors":"A. Atrash, G. Cassuto, W. Chen, V. Dayan, O. Galzur, M. Gutman, A. Heiman, G. Hunsinger, D. Nahmad, A. Parag, E. Pikhay, Y. Roizin, B. Smith, A. Strum, T. Tishbi, R. Teggatz","doi":"10.1109/IMW.2010.5488313","DOIUrl":null,"url":null,"abstract":"A zero-cost embedded high density MTP NVM with extensive statistical verification is presented. The family of compact single Poly modules ranging from 64bit to 64kbit is based on the Y-Flash concept, employing original array architectures and implemented in standard and power management (PM) 0.18um CMOS process flows. No special HV devices or additional masks are employed. Excellent reliability performance allowing more than 10k program/erase cycles and 10year data retention at 150°C is demonstrated.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Zero-cost MTP high density NVM modules in a CMOS process flow\",\"authors\":\"A. Atrash, G. Cassuto, W. Chen, V. Dayan, O. Galzur, M. Gutman, A. Heiman, G. Hunsinger, D. Nahmad, A. Parag, E. Pikhay, Y. Roizin, B. Smith, A. Strum, T. Tishbi, R. Teggatz\",\"doi\":\"10.1109/IMW.2010.5488313\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A zero-cost embedded high density MTP NVM with extensive statistical verification is presented. The family of compact single Poly modules ranging from 64bit to 64kbit is based on the Y-Flash concept, employing original array architectures and implemented in standard and power management (PM) 0.18um CMOS process flows. No special HV devices or additional masks are employed. Excellent reliability performance allowing more than 10k program/erase cycles and 10year data retention at 150°C is demonstrated.\",\"PeriodicalId\":149628,\"journal\":{\"name\":\"2010 IEEE International Memory Workshop\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-05-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Memory Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW.2010.5488313\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2010.5488313","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Zero-cost MTP high density NVM modules in a CMOS process flow
A zero-cost embedded high density MTP NVM with extensive statistical verification is presented. The family of compact single Poly modules ranging from 64bit to 64kbit is based on the Y-Flash concept, employing original array architectures and implemented in standard and power management (PM) 0.18um CMOS process flows. No special HV devices or additional masks are employed. Excellent reliability performance allowing more than 10k program/erase cycles and 10year data retention at 150°C is demonstrated.