D. Gilmer, K. Lim, H. Park, C. Park, N. Goel, P. Kirsch, R. Jammy
{"title":"Impact of plasma gate reoxidation on the non-volatile charge trap memory device","authors":"D. Gilmer, K. Lim, H. Park, C. Park, N. Goel, P. Kirsch, R. Jammy","doi":"10.1109/IMW.2010.5488408","DOIUrl":null,"url":null,"abstract":"Post gate-etch reoxidation in plasma H2/O2 was successfully employed to non-volatile TANOS charge-trap memory devices without any adverse oxidation on the TaN gate-electrode sidewall. Using this plasma reoxidation process showed significant device improvement in the narrow gate retention and endurance characteristics. This improvement is thought to result from gate etch damage repair, and locally thicker tunnel oxide formation near the gate edge, from the plasma reoxidation process. Circumventing gate etch damage will be indispensable for sub-30nm charge-trap flash memory devices.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2010.5488408","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Post gate-etch reoxidation in plasma H2/O2 was successfully employed to non-volatile TANOS charge-trap memory devices without any adverse oxidation on the TaN gate-electrode sidewall. Using this plasma reoxidation process showed significant device improvement in the narrow gate retention and endurance characteristics. This improvement is thought to result from gate etch damage repair, and locally thicker tunnel oxide formation near the gate edge, from the plasma reoxidation process. Circumventing gate etch damage will be indispensable for sub-30nm charge-trap flash memory devices.