International Symposium on Microelectronics最新文献

{"title":"Lithography Solutions for Submicron Panel-Level Packaging","authors":"Doug Shelton","doi":"10.4071/1085-8024-2021.1.000093","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000093","url":null,"abstract":"\u0000 Heterogeneous Integration of logic, memory, photonic, analog and other value-adding functions is one approach for increasing electronic system efficiency, performance and bandwidth while helping reduce overall manufacturing costs. To capitalize on Heterogeneous Integration benefits, designers are requiring finer resolution Redistribution Layer patterning and larger package sizes to maximize System-in-Package integration possibilities.\u0000 Production of large-package electronics systems is well-suited for Panel Level Packaging (PLP) and achieving uniform submicron patterning across the entire rectangular panel is a key lithography challenge. To meet this challenge, Canon developed the first lithography exposure system or stepper that is capable of achieving submicron resolution on 500 mm panels. The stepper features a panel handling system for processing panels up to 515 mm x 515 mm in size and is also equipped with wide-field projection lens featuring a maximum 0.24 Numerical Aperture and a large 52 mm x 68 mm image field.\u0000 This paper will report on evaluation results for a submicron PLP process using the panel stepper and will introduce high-resolution PLP process challenges including warped panel handling. Process results on Copper Clad Laminate (CCL) substrates will be reported including pattern uniformity, adjacent shot stitching accuracy and overlay accuracy on substrates containing die-placement error that is common in Fan-Out processes.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"2 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74378151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Substrate-less Process for Heterogeneous Integration of mm-Wave Circuits","authors":"C. Crump, Yihang Chu, P. Chahal","doi":"10.4071/1085-8024-2021.1.000224","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000224","url":null,"abstract":"\u0000 In this paper, a new ultra-compact substrate-less approach to heterogeneous integration of millimeter wave circuits is demonstrated. In the proposed process, active and passive components are placed face down on a temporary carrier. A thick layer of benzocyclobutene (BCB) is deposited surrounding these components using aerosol jet printing (AJP). This is followed by a combination of the blanket deposition of silver conductor and perforated BCB layers. This approach allows for the placement of chips close to each other leading to heterogeneous integration. Also, the front side is made planar, which allows for subsequent processing of low-loss interconnects. Here, as a proof of concept, a simple interconnect between two chips, placed close to each other, is demonstrated.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"2 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79024379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Characterization of All Inorganic and Organic Components in Neutral Tin Plating Bath for Electronics Applications","authors":"E. Shalyt, Jingjing Wang, Vishal Parekh, Chuannan Bai, Guang Liang","doi":"10.4071/1085-8024-2021.1.000271","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000271","url":null,"abstract":"\u0000 Tin plating at neutral and near-neutral pH is the preferable process in the application of electronic components such as capacitors and resistors, where the chemically sensitive ceramic and glass portions can be damaged by highly acidic solutions (often used in semiconductor packaging processes). Stannous ions are not as stable at elevated pH due to oxidation and hydrolysis, and plating demands the use of a large number of additives making the process control very challenging. Various analytical techniques are developed for automatic and comprehensive characterization of all inorganic and organic bath components including simultaneous detection of conductive salt, anti-whisker and chelator by near-infrared (NIR) spectroscopy, brightener by potentiometric titration, stannous ions by electrochemical method, and the breakdown stannic ions by spectro-titration.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"15 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75168871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine Line and Low Stress RDL Solition for Fan-Out Wafer Level & Panel Level Packaging","authors":"Yoshinori Matsuura, T. Yoshida, Yukiko Komiya, Toshimi Nakamura, Takenori Yanai, Kazuhiro Okuyama, Yukiko Kitabatake, Rintaro Ishii, Katsuyuki Hayashi, Takashi Kubota, Joji Fujii","doi":"10.4071/1085-8024-2021.1.000039","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000039","url":null,"abstract":"\u0000 Process limitations faced during the construction and integration of current and next generation advanced packages require a new RDL (Redistribution Layer) approach to overcome fine L/S and stress constraints. If interactions between design, process and materials are not optimized or controlled, then yield loss and higher cost result. RDL is an integral part of a package and with greater design complexity the number of such layers also increase.\u0000 This paper introduces a new RDL concept through HRDP® (High Resolution Debondable Panel) technology. It has received industry wide attention, especially for Fan-Out, Chip Last, Wafer Level & Panel Level package assemblies. The structure and materials for HRDP® are described. The applicable HRDP® carrier can be provided in various dimensions and thicknesses for round panels and for square/rectangular panels with glass or silicon to match customer requirements. This accommodates process simplification and improves interfacial stresses. The process steps using HRDP® are elaborated, which essentially use existing tools in RDL metal patterning (i.e., Lithography, Developer/Descum etc.) without disrupting the assembly line layout and process flow.\u0000 HRDP® is compatible with existing dielectrics and photoresists. It has been demonstrated that based upon the capabilities of dielectrics and photoresists used for RDL in the bump fab, fine L/S geometries of 2/2 um and less have been achieved. Reliability data has been shared.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"41 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85250499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced UVA LED-Cured Conformal Coatings for Printed Circuit Boards","authors":"N. Pfeiffenberger, Saeid Biria","doi":"10.4071/1085-8024-2021.1.000281","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000281","url":null,"abstract":"\u0000 Conformal coatings are thin polymeric layers applied on (RF)/microwave printed circuit boards, chips, dies and other electronic components to protect them from moisture and corrosion. Despite this protection, exposure to excessive humidity can cause delamination, increase dissipation factors and dielectric constants of the coating, and changing circuit switching-speed. In this paper, we will discuss dielectric performance of UVA LED-curable resin formulations with enhanced flexibility and adhesion as a new approach compared to traditional mercury UV curable conformal coatings. These advances reduce the potential for delamination, delivering greater protection of different applications, especially those for extreme environments.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"73 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91169278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced wire bonding standards for European automotive and power electronics industry","authors":"S. Schmitz, M. Schneider-Ramelow","doi":"10.4071/1085-8024-2021.1.000339","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000339","url":null,"abstract":"\u0000 This article presents the wire bond standard DVS-2811, which is widely used in German-speaking and European countries. Introduced in 1996, this standard now contains definitions and limits for all currently used bonding methods, including the shear test on heavy/thick wire bond connections, which is missing in all other official standards. Especially considering the growing number of users in battery bonding, the specification of appropriate limits for testing thick wires is of important significance. In addition to an overview of the current status, an outlook is given on further updates that are due in the next 1–2 years.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"69 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84705585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability of Chiplets Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill","authors":"Ricky Tsun-Sheng Chou, J. Lau, G. Chen, J. Huang, C. Yang, H. Liu, T. Tseng","doi":"10.4071/1085-8024-2021.1.000124","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000124","url":null,"abstract":"\u0000 In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"2 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86051923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memory Packaging Challenges for a Growing Market","authors":"Knowlton Olmstead, C. Zwenger, R. Strode","doi":"10.4071/1085-8024-2021.1.000207","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000207","url":null,"abstract":"\u0000 Increasing demands for storage and high-performance memory in applications such as artificial intelligence (AI), machine learning and processing storage are driving long-term growth in the market. This paper will highlight the key challenges encountered in packaging next-generation memory devices and discuss some of the technological developments required to address them while considering performance, cost, and yield. An evaluation is highlighted of a remote microwave plasma process to remove damage caused by laser ablation during the wafer dicing process that shows an improvement in die strength using this process.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"27 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74774272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of Al Heavy Wire Bonds Bond profile in WBG Power Module Design","authors":"U. Mehrotra, Adam J. Morgan, D. Hopkins","doi":"10.4071/1085-8024-2021.1.000260","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000260","url":null,"abstract":"\u0000 Wide-Band Gap (WBG) semiconductors, such as SiC and GaN, have accelerated the ability to shrink the volumetric size and weight of power conversion systems by optimizing at the module level, due to their inherent high frequency, high temperature and high voltage capabilities. Power electronic module components, specifically flexible welded interconnects, behave like transmission lines at higher frequencies. Therefore, interconnects contribute to the power losses within the power module, and ultimately affect overall efficiency. Voltage and current overshoots and insertion/return losses and phenomena such as proximity and skin effect will also have a noticeable effect on the performance of the module as device switching is pushed into mid to high MHz range. Thus, to aid in design and development of advanced power modules this paper using FEA multiphysics solvers will firstly study the current carrying capacity and fusing time of different diameter Al heavy wire bonds interconnects. Then for a rated current, the multiple wire bond profile is considered to mitigate the negative effects from the fastest rising/fall edge of voltage and current switching high-frequency components. Characteristic impedance is then calculated using parasitic resistance and inductance for different wire bond profiles. The ultimate goal of the paper is to further the establishment of an evolution in thinking and designing when it comes to the WBG power electronic packaging practices and culture.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"12 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84798381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges and novel approaches for the development of hardware-related trustworthy electronics","authors":"A. Middendorf, M. Böttcher, E. Jung, H. Pötter, I. Ndip, M. Töpper, M. Schneider-Ramelow, W. Steller","doi":"10.4071/1085-8024-2021.1.000376","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000376","url":null,"abstract":"\u0000 Emerging and future electronic components and systems must not only meet cost, performance, reliability, miniaturization and environmental requirements, they must also be trustworthy. In the near future, we have to trust even more electronic components and systems in everyday life, such as those used in self-driving cars or service robots.\u0000 In this contribution, we present the challenges and novel approaches for the development of hardware-related trustworthy electronics. Our proposed solutions cover all aspects of the value chain starting with the confidentiality of secure production chains, the security against manipulation as well as technological sovereignty. These novel approaches are extensively investigated with partners from academia and industry in R&D projects within the framework of the German Flagship initiative “Trustworthy Electronics”. The German Federal Ministry of Education and Research (BMBF) as a contribution to research and innovation for technological sovereignty fund this initiative.\u0000 In this paper, we will report on the latest research results of the implementation of our approaches at four key levels, namely wafer, board, system and platform levels.\u0000 In the area of wafer level packaging, the focus is on developing solutions for the implementation of trustworthy heterogeneous systems using high-frequency chips in combination with complex signal processing.\u0000 At board-level, the goal is to develop a universal electro-optical interposer, particularly taking into account security features (e.g. key generation and encryption / decryption, design of photonic expandable RISC-V peripheral components).\u0000 At system-level, we focus on the development of processes and multi-sensor systems that protect important microelectronic circuits from criminal attacks. The entire system has to be protected by hierarchically graded monitoring, by embedded sensors and its corresponding microcontrollers. The development of the packaging and interconnection technology is supplemented by non-destructive testing methods that monitor the integrity of the protective mechanisms. The approach pursued here does not require any modification of the structure of the circuits to be protected and can be combined with all safety-critical application circuits. With this cost-effective solution, small series production is also economically feasible.\u0000 Finally, at the platform-level, overreaching issues are investigated within the three pillars, namely design, production and analysis of the microelectronic value chain. The platform concentrates predominantly on contributions to the necessary standardization. This enables companies effectively to support the supply of trustworthy electronics, especially with regard to small series.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"5 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80366596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}