International Symposium on Microelectronics最新文献

{"title":"Coronavirus, chip boom, and supply shortage: The new normal for global semiconductor manufacturing","authors":"Stephen M. Rothrock","doi":"10.4071/1085-8024-2021.1.000026","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000026","url":null,"abstract":"\u0000 Over the past 50 years, the semiconductor industry has faced its fair share of difficult challenges. The COVID-19 pandemic the world is currently experiencing has caused the worst downturn since the financial crisis of 2008, devastating global economies. And yet, the semiconductor industry has repeatedly shown incredible resilience in the face of adversity. Despite the pandemic, the market has not experienced such a dramatic upturn since 2003 and as a result, the new market upturn breaks open the fundamental flaws and risks of manufacturing concentration and outsourcing.\u0000 At a time when the world is precariously dependent on Taiwan for semiconductors, how can the global supply chain forecast, manage, and plan for such sudden shifts in the future? Now more than ever before, advanced technology companies need to keep the finger on the pulse of supply and demand to successfully inform their strategic manufacturing decisions and remain agile to ensure continuity of supply. As chip demand booms in the midst of a supply shortage over the coming months and supply is no longer a given, what does the future hold for manufacturing fabs? Will greenfield become the rule rather than the exception in this new normal? How will the market upturn impact global fab location choices?\u0000 Reflecting on some 20 years of experience completing international semiconductor manufacturing asset transactions in North America, Europe, and Asia, ATREG Founder, President, and CEO Stephen M. Rothrock will provide insights into the current global manufacturing asset market and how it is likely to evolve as part of the current market upturn.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"66 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73795898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chiplets Heterogeneous Integration on High-Density Hybrid Substrate Using an Interconnect-Layer","authors":"C. Peng, J. Lau, C. Ko, Paul Lee, E. Lin, Kai-Ming Yang, P. Lin, Tim Xia, Leo Chang, N. Liu, Curry Lin, T. Lee, Jason Wang, M. Ma, T. Tseng","doi":"10.4071/1085-8024-2021.1.000217","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000217","url":null,"abstract":"\u0000 In this study, a high-density organic hybrid substrate for chiplets heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication, and characterization of the hybrid substrate with an interconnect-layer. A non-linear finite element analysis is performed to show the state of stress at the vias filled with a conductive paste of the interconnect-layer.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"30 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77687465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal and Reliability Performance Comparison of DBC-Based and Organic-Based Double-Sided Cooled Power Modules","authors":"Tzu-Hsuan Cheng, Kenji Nishiguchi, Y. Fukawa, D. Hopkins","doi":"10.4071/1085-8024-2021.1.000382","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000382","url":null,"abstract":"\u0000 Direct Bonded Copper (DBC) is the most popular solution for conventional high-power modules because of superior thermal/electrical/mechanical performance and mature manufacturing. To meet the rising demand of power density and power rating, a Double-Sided Cooled (DSC) sandwich structure using dual insulated metal-clad substrates was proposed and DBC still dominated the substrate selection of DSC power modules. However, there are several long-existing reliability challenges of conventional DBC-based power modules and the cost of DBC is relatively high compared with organic and metal (e.g. lead frame) substrates. This study proposes a DSC 1.2 kV half-bridge power module using dual epoxy-resin Insulated Metal Substrate (eIMS) for solving DBC-based power module issues and providing a cost-effective solution. The thermal performance outperforms traditional Alumina (Al2O3) DBC-based DSC power module due to moderate thermal conductivity (10 W/mK) and thin (120 μm) epoxy-resin composite dielectric layer compared with Alumina. The breakdown voltage of this high thermally conductive organic dielectric is 5 kVAC (@ 120 μm) and the Glass Transition Temperature (Tg) is 300°C which is indispensable for Wide-Band-Gap (WBG) devices and high-power applications. In terms of thermal-mechanical reliability, the organic-based DSC power module can pass the thermal cycling test over 2000 cycles by optimizing the mechanical properties of the encapsulant material. In conclusion, this paper not only proposes a competitive organic-based power module but also a methodology of evaluation for thermal and mechanical performance.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"25 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83980754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Accuracy Pick-and-Place of Multiple Dies in Parallel Assisted by Capillary Self-Alignment","authors":"Birgit Brandstätter, B. Auer, H. Klingler, S. Scherbaum","doi":"10.4071/1085-8024-2021.1.000074","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000074","url":null,"abstract":"\u0000 Self-assembly of components driven by liquid surface tension is an attractive complement and even alternative to traditional high-accuracy pick-and-place as it offers high accuracy despite inaccurate robotic part placement. While capillary self-alignment through liquid solder is the standard technology for flip-chip processes, this work presents self-alignment of dies on wetted receptors on a temporary carrier: Low-viscosity liquid is jetted on each receptor where the liquid is contained through generation of hydrophilic and hydrophobic sections on the temporary carrier by plasma treatment. Deterministic die feeding by low-accuracy pick-and-place is conducted for single dies, as well as for batches of three dies and nine dies optimizing the equipment for best throughput to achieve both high accuracy and high productivity. The industry-ready and fully automated chip-to-wafer pick-and-place process is implemented into a fan-out wafer-level packaging production flow proving that self-alignment is capable of easing the stringent requirement for robotic alignment capability for pick-and-place systems in fan-out packaging for the single die-level step in this production chain. The self-alignment process is optimized, and failure modes such as poor liquid confinement, surface contamination, or excess force are identified and eliminated. Post-bond accuracy of <3 μm @ 3 σ at each point of the die is reached for dies of 3.1 mm x 3.1 mm in size. Using parallel die handling, high speeds of around 10 000 units per hour are made possible.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"32 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82853847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MAXQFP: NXP's new package solution for automotive application","authors":"C. Lee, T. Tran, A. Mawer, Xs Pang, J. Yao","doi":"10.4071/1085-8024-2021.1.000015","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000015","url":null,"abstract":"\u0000 172-lead (16x16 mm body size) and 100-lead (10x10 mm body size) MAXQFP's and 172 MAXQFP_EP (exposed pad) for automotive industry are introduced. The advantage of MAXQFP as compare to standard LQFP/QFP packages will be outlined. Thermal & mechanical simulation results were performed to prove its advantage over conventional LQFP and LQFP_EP. The challenges in manufacturing, designs and concerns of tighter lead pitches for MAXQFP are briefly addressed. Methods and data to resolve these challenges will be shown. For example, Sn whisker and Sn migration both are concerns to MAXQFP because of smaller distance between adjacent leads. The board-level solder joint reliability (SJR) has been collected to prove it is AEC G1 compliant. Visual inspection methods and requirements on AOI (automatic object inspection) systems on solider joints of J-leads of MAXQFP for are proposed. Standard AEC G1 component level reliability stresses defined at AEC Q100 which are TC (temperature cycling), HTSL (high temperature storage life), THB (Temperature Humidity Biased) and uHAST (un-biased HAST) tests are summarized Since Cu wires were used, AEC Q006 data are also collected. Assembly challenges are described. Future works will be summarized.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"631 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78980537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Design of High-Temperature Lead-Free Solders for Die-Attachment in Power Discrete Applications","authors":"HongWen Zhang, Samuel Lytwynec, Huaguang Wang, J. Geng, Francis Mutuku, N. Lee","doi":"10.4071/1085-8024-2021.1.000356","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000356","url":null,"abstract":"\u0000 Development of high-temperature lead-free (HTLF) solders to replace high-lead solders for die-attachment in power device applications is driven by (1) the harmful effects of lead to human health and the environment, and (2) the demand of the improved bonding materials serving under high-power density and high-junction temperatures, especially for wide-band-gap power devices. A novel design, based on a mixed solder powder paste technology—Durafuse™—has been developed to deliver a Sn-rich HTLF paste, presenting the merits of both constituent powders. The combination of the rigid, high-melting SnSbCuAgX and the ductile, low-temperature Sn-rich solder in one paste enables reflow at a relatively low temperature (barely above the liquidus temperature of the final joint composition) and maintains the joint strength above 15MPa in the temperature range between 270°C and 295°C. The sufficient high-temperature strength has demonstrated the capability of maintaining the joint integrity during subsequent multiple SMT reflows below the 270°C peak temperature, regardless of the existence of a partial melting phase. Both X-ray inspection and cross-section microstructure have not shown any damage in the Si die or any noticeable cracks in the bonding joint, even after 3000 cycles of TCT (−40 to 150°C). In summary, Durafuse™ HT, the novel design of the high-temperature lead-free pastes, has shown the feasibility as a drop-in solution to replace high-lead solders for die-attachment in power discrete applications.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"155 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86208763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stabilized Sanathanan-Koerner Iteration for Rational Transfer Function Approximation of Scattering Parameters","authors":"Andrew Ma, Daniel Deaton, A. Engin","doi":"10.4071/1085-8024-2021.1.000171","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000171","url":null,"abstract":"\u0000 The vector-fitting algorithm has been the predominant method of macromodeling of high-frequency circuits for the past 20 years. Vector fitting is based on a partial-fractions basis to avoid the ill-conditioning of the Vandermonde matrices in direct fitting of the polynomial coefficients of a rational function. In a recent formulation of the Sanathanan- Koerner iteration, an orthogonal basis is obtained using the Arnoldi iteration significantly improving the conditioning and accuracy of rational approximation. This Stabilized Sanathanan-Koerner (SSK) iteration has been mostly applied on closed-form functions or data with no noise. We will utilize this SSK formulation for high-frequency package interconnect macromodeling. The method will be tested using empirical scattering parameters on a noisy transmission line system. The resultant curve fit will then be compared to several other polynomial and rational linear approximation methods, including the standard polynomial approximation. We show that the SSK method compares favorably to these different methods and provide a curve fit that can provide a reasonable approximation over different frequency ranges.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"10 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88212799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Burn-in-Testing (BIT) Challenge: to BIT or not to BIT?","authors":"E. Suhir","doi":"10.4071/1085-8024-2021.1.000031","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000031","url":null,"abstract":"\u0000 Burn-in testing (BIT) is a costly undertaking. Predictive modeling enables shading useful light on what and how should be tested, if at all. Three analytical (“mathematical”) predictive models recently suggested by the author are addressed in this mini-review: 1) A model based on the analysis of the infant mortality portion (IMP) of the bathtub curve (BTC) suggests that the non-random time derivative of the expected “statistical” failure rate (SFR) at the beginning of the IMP could be viewed as a suitable criterion (“figure of merit”) to answer the basic question of the BIT undertaking: “to BIT or not to BIT?” 2) A model based on the analysis of the random failure rate (RFR) of the mass-produced components that the manufactured product of interest is comprised of suggests that the above derivative is, in effect, the RFR variance of these components. 3) A model based on the use of the kinetic multi-parametric Boltzmann-Arrhenius-Zhurkov (BAZ) constitutive equation is employed to establish the BIT's adequate duration and level, if this kind of failure-oriented-accelerated-testing (FOAT) is found to be necessary. The theoretical findings are illustrated by calculated data. It is concluded that predictive modeling should always precede the actual BIT, that analytical modeling should always complement computer simulations and that future work should address the experimental validation and possible extension of the obtained results and recommendations.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"36 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91175639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancing the Paste Release on 55μm pads with Water-Soluble Type 7 SAC305 Solder Paste for High Density SIP Application","authors":"B. Senthil Kumar, Zhang Rui Fen, Yam, Lip Huei, Zhang HanWen, Kang Sungsig, Chan Li-san","doi":"10.4071/1085-8024-2021.1.000239","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000239","url":null,"abstract":"\u0000 The ultra-fine SAC305 solder is widely used as the lead-free solder composition for interconnection in advanced packaging based on its advantages such as good joint strength, thermo-mechanical fatigue behavior and creep resistance. Stencil printing remains the technology of choice for system-in-package (SiP) assembly because of its benefits such as economy of usage, ease of process control, flexibility of usage and fast and wide range of process window.\u0000 SiP involves the high-level integration of different components, Copper (Cu) pillar flip-chip dies and chips in one package to achieve multiple functions in one system. The need to accommodate ever increasing demand for reduced footprints requires the technology to constantly invent a range of Cu pillar 55μm diameter and smaller components. Many mobile communications SiP consist of 6 or more flip chips in a single package. Conventional flip-chip attach uses flux & Cu pillar solder cap for solder joint formation as it is challenging for solder paste to be printed on fine geometries below 70μm. Additional benefits of solder paste printing help eliminate non-wet Cu pillar defect rates and improve yield over conventional flux printing. Heraeus solder paste (AP series T7) makes use of ultra-fine spherical shape of solder powder to create strong metal coalesce for bonding during reflow process of Cu pillars mounting to substrates.\u0000 For example, the smallest passive component in use today is 008004 and Cu pillar diameter of 70um, which has a stencil opening of 125μm and 70μm respectively. Further reduction in Cu pillar flip-chip diameter of 55μm will require further reduction in stencil opening to 55μm, thus testing the limits of current type 7 pastes. Current solder pastes (AP series T7) can meet the consistency of printability when the stencil opening is 70μm or more. With smaller stencil opening, down to 55μm, the printing performance is less than desired. In this paper we describe the stencil printing application on the enhanced version of type 7 paste with a reinvented flux. The application tests were carried out using 55μm stencil opening. This paper will report the results of this application test.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"74 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72961838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New approach for High Reliable & Cost-Effective Solder alloys for Automotive Applications","authors":"S. Fritzsche, Manu Noe Vaidya, P. Prenosil, Katja Stenger, Jörg Trodler, M. Jörger","doi":"10.4071/1085-8024-2021.1.000159","DOIUrl":"https://doi.org/10.4071/1085-8024-2021.1.000159","url":null,"abstract":"\u0000 Commercially known as Innolot, the highly reliable lead-free alloy, allowing for high operating temperatures, is a Tin-Silver-Copper (SAC) metallurgical system with additional elements to harden the alloy and to improve its creep strength in order to significantly improve the reliability of solder joints. Compared to traditional SAC alloys, the characteristic lifetime can be enhanced on the base of temperature cycle tests (TCT) from −40°C to +125°C or even extended to 150°C.\u0000 Assemblies in the automotive industry increasingly require higher reliability for safety relevant and emerging applications such as Advanced Driver Assistance Systems (ADAS). Cost-reduction requirements demand a new approach for optimized soldering processes and materials. As the current reflow process prefers Nitrogen atmosphere for low defects in high reliability soldering, our research focuses around the partial and/or complete change to air soldering processes. Furthermore, we investigate the influence of different surface finishes such as Chemical Sn, NiAu, and Cu OSP, and modified alloy compositions in the soldering performance. Apart from initial characterizations for various assemblies, reliability tests on Heraeus Reliability1 printed circuit boards as well as temperature cycle tests from −40 to +150°C for up to 2500 cycles are reported and resulting failure modes are discussed.\u0000 This paper furthermore describes the potential for cost reductions via process and/or material optimizations without diminishing the high reliability performance for such automotive applications.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"39 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80139283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}