Ricky Tsun-Sheng Chou, J. Lau, G. Chen, J. Huang, C. Yang, H. Liu, T. Tseng
{"title":"基于焊点和衬底的2.3 3d杂化衬底上小片异质集成可靠性研究","authors":"Ricky Tsun-Sheng Chou, J. Lau, G. Chen, J. Huang, C. Yang, H. Liu, T. Tseng","doi":"10.4071/1085-8024-2021.1.000124","DOIUrl":null,"url":null,"abstract":"\n In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"2 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Reliability of Chiplets Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill\",\"authors\":\"Ricky Tsun-Sheng Chou, J. Lau, G. Chen, J. Huang, C. Yang, H. Liu, T. Tseng\",\"doi\":\"10.4071/1085-8024-2021.1.000124\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\n In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.\",\"PeriodicalId\":14363,\"journal\":{\"name\":\"International Symposium on Microelectronics\",\"volume\":\"2 1\",\"pages\":\"\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium on Microelectronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.4071/1085-8024-2021.1.000124\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4071/1085-8024-2021.1.000124","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reliability of Chiplets Heterogeneous Integration on 2.3D Hybrid Substrate Using Solder Joint and Underfill
In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.