Lithography Solutions for Submicron Panel-Level Packaging

Abstract

Heterogeneous Integration of logic, memory, photonic, analog and other value-adding functions is one approach for increasing electronic system efficiency, performance and bandwidth while helping reduce overall manufacturing costs. To capitalize on Heterogeneous Integration benefits, designers are requiring finer resolution Redistribution Layer patterning and larger package sizes to maximize System-in-Package integration possibilities. Production of large-package electronics systems is well-suited for Panel Level Packaging (PLP) and achieving uniform submicron patterning across the entire rectangular panel is a key lithography challenge. To meet this challenge, Canon developed the first lithography exposure system or stepper that is capable of achieving submicron resolution on 500 mm panels. The stepper features a panel handling system for processing panels up to 515 mm x 515 mm in size and is also equipped with wide-field projection lens featuring a maximum 0.24 Numerical Aperture and a large 52 mm x 68 mm image field. This paper will report on evaluation results for a submicron PLP process using the panel stepper and will introduce high-resolution PLP process challenges including warped panel handling. Process results on Copper Clad Laminate (CCL) substrates will be reported including pattern uniformity, adjacent shot stitching accuracy and overlay accuracy on substrates containing die-placement error that is common in Fan-Out processes.