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A high-speed lossless embedded compression codec for high-end LCD applications 用于高端LCD应用的高速无损嵌入式压缩编解码器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708759
Yu-Hsuan Lee, Yu-Yu Lee, Huang-Zueng Lin, T. Tsai
{"title":"A high-speed lossless embedded compression codec for high-end LCD applications","authors":"Yu-Hsuan Lee, Yu-Yu Lee, Huang-Zueng Lin, T. Tsai","doi":"10.1109/ASSCC.2008.4708759","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708759","url":null,"abstract":"Due to the great evolution of LCD panel technology, the memory bandwidth of display media system is significantly increased. Its impact on system cost, EMI of transmission interface, and memory bandwidth almost dominates the performance of entire display media system. To eliminate this effect, a high-speed lossless embedded compression algorithm with pipelining and parallel VLSI architecture is proposed. With associated geometric-based probability model (AGPM), the compact coding flow is constructed by geometric-based binary code and content-adaptive Golomb-Rice code to achieve high-speed capability. The entire codec is implemented by TSMC 0.18-mum 1P6M CMOS technology with Artisan cell library. The processing capability of two-level parallelism achieves Full-HD 1080p@60 Hz with RGB components, and the four-level parallelism can further support 120 Hz double frame rate (DFR) technique for high-end LCD applications.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132022911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 50Mbps double-binary turbo decoder for WiMAX based on bit-level extrinsic information exchange 基于位级外部信息交换的50Mbps WiMAX双二进制turbo解码器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708788
Ji-Hoon Kim, I. Park
{"title":"A 50Mbps double-binary turbo decoder for WiMAX based on bit-level extrinsic information exchange","authors":"Ji-Hoon Kim, I. Park","doi":"10.1109/ASSCC.2008.4708788","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708788","url":null,"abstract":"A 50 Mbps, 2.24 mm2 double-binary turbo double decoder is designed and implemented in 0.13 mum CMOS process for the WiMAX standard. To reduce the large extrinsic memory needed in double-binary turbo decoding, the proposed decoder exchanges the bit-level extrinsic information values rather than the traditional symbol-level extrinsic information values, which is achieved by deriving two simple conversions. The proposed turbo decoder, with a low-complexity hardware interleaver generating interleaved addresses for two data flows simultaneously, provides an efficient stopping criterion for double-binary turbo decoding using bit-level extrinsic information as well as huge memory size reduction of 20.6%.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123465851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 8 GByte/s transceiver with current-balanced pseudo-differential signaling for memory interface 一个8gbyte /s的收发器，具有电流平衡的伪差分信号，用于内存接口
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708772
Seon-Kyoo Lee, Dong-Woo Jee, Yunjae Suh, Hong-June Park, J. Sim
{"title":"A 8 GByte/s transceiver with current-balanced pseudo-differential signaling for memory interface","authors":"Seon-Kyoo Lee, Dong-Woo Jee, Yunjae Suh, Hong-June Park, J. Sim","doi":"10.1109/ASSCC.2008.4708772","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708772","url":null,"abstract":"A 8 GByte/s single-ended parallel transceiver is implemented in a 0.18 mum standard CMOS with a current-balanced pseudo-differential signaling for high-speed memory interface. With a segmented group-inversion coding, 16-bit data is encoded to 20 pins for dramatic reduction of simultaneous switching noise which has been a bottleneck in high-speed parallel links. The proposed pseudo-differential signaling achieves a power-efficient current-mode parallel termination with a reduction of driving current of about 40-percent. For the termination, virtual voltage sources are self-generated by tracking the center of eye opening. The transceiver shows a BER of less than 10-12 at 4 Gb/s/pin.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127305648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 21.2μA ΔΣ-based interface ASIC for a capacitive 3-axis micro-accelerometer 一种21.2μA ΔΣ-based接口的电容式三轴微加速度计专用集成电路
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708739
M. Paavola, M. Kamarainen, E. Laulainen, M. Saukoski, L. Koskinen, M. Kosunen, K. Halonen
{"title":"A 21.2μA ΔΣ-based interface ASIC for a capacitive 3-axis micro-accelerometer","authors":"M. Paavola, M. Kamarainen, E. Laulainen, M. Saukoski, L. Koskinen, M. Kosunen, K. Halonen","doi":"10.1109/ASSCC.2008.4708739","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708739","url":null,"abstract":"In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer implemented in a 0.25-mum CMOS process is presented. The fully-integrated sensor interface consists of a DeltaSigma sensor front-end that converts the acceleration signal into the digital domain, a decimator, a frequency reference, a clock generator for the front-end, a voltage and current reference, the required reference buffers, and low-dropout regulators (LDOs) needed for system-on-chip power management. The interface IC provides operating modes for 1 and 25 Hz signal bandwidths. The chip with a 1.72 mm2 active area draws 21.2 muA in 1 Hz mode, and 97.6 muA in 25 Hz mode, from a 1.2-2.75 V supply. In 1 Hz mode with a plusmn2 -g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 1080, 1165 and 930 mug/radicHz, respectively.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128022101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A wideband CMOS variable gain low noise amplifier based on single-to-differential stage for TV tuner applications 一种用于电视调谐器的基于单差分级的宽带CMOS可变增益低噪声放大器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708826
Kefeng Han, Liang Zou, Youchun Liao, Hao Min, Zhangwen Tang
{"title":"A wideband CMOS variable gain low noise amplifier based on single-to-differential stage for TV tuner applications","authors":"Kefeng Han, Liang Zou, Youchun Liao, Hao Min, Zhangwen Tang","doi":"10.1109/ASSCC.2008.4708826","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708826","url":null,"abstract":"A wideband CMOS variable gain low noise amplifier (VGLNA) used for TV tuner is presented. A single-to-differential (S2D) circuit other than an off-chip balun is applied for high gain mode and a resistive attenuator is for five steps (6 dB per step) attenuation in low gain mode. The performance of S2D, especially the noise factor is analyzed. The chip is implemented in a 0.18-mum 1P6M mixed-signal CMOS process. Measurements show that in the 50-860 MHz frequency range, the VGLNA achieves 15 dB maximum gain, 31 dB variable gain range, a minimum 3.8 dB noise figure and 2.6 dBm 11P3 at 15 dB gain while consumes 5.7 mA from a 1.8 V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126915849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A 16Gb/s 65nm CMOS transceiver for a memory interface 内存接口采用16Gb/s 65nm CMOS收发器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708720
J. Chun, Haechang Lee, Jie Shen, T. Chin, Ting Wu, Xudong Shi, K. Kaviani, W. Beyene, B. Leibowitz, R. Perego, K. Chang
{"title":"A 16Gb/s 65nm CMOS transceiver for a memory interface","authors":"J. Chun, Haechang Lee, Jie Shen, T. Chin, Ting Wu, Xudong Shi, K. Kaviani, W. Beyene, B. Leibowitz, R. Perego, K. Chang","doi":"10.1109/ASSCC.2008.4708720","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708720","url":null,"abstract":"A transceiver for a memory controller operating at 16 Gb/s per link is implemented in 65 nm CMOS process. Timing calibration, equalization and diagnostic circuits for both memory read and write are on the controller to optimize the overall system performance and cost. A 5-tap TX FIR and a continuous time RX equalizer with active inductor loads are employed. The transceiver also includes a diagnostic circuit which can add a programmable DC differential voltage offset and produce actual eye diagrams for both write and read links. It is demonstrated that each link can operate at 16 Gb/s with a timing margin of 0.19 UI at a BER of 10-12.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128230033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit 用65nm CMOS速度监控电路测量片上数字Idn和Idp
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708813
H. Notani, M. Fujii, H. Suzuki, H. Makino, H. Shinohara
{"title":"On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit","authors":"H. Notani, M. Fujii, H. Suzuki, H. Makino, H. Shinohara","doi":"10.1109/ASSCC.2008.4708813","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708813","url":null,"abstract":"An on-chip digital I<sub>ds</sub> measurement method is proposed in this report. In the proposed method, I<sub>ds</sub> is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS I<sub>ds</sub> (I<sub>dn</sub>) and PMOS I<sub>ds</sub> (I<sub>dp</sub>) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first I<sub>ds</sub> calculated from measured frequencies, and the second I<sub>ds</sub> directly measured for reference, was analyzed. The standard deviations of the mismatch error in I<sub>dn</sub> and I<sub>dp</sub> are 1.64% and 1.09%, respectively. The margin of 3sigma is within 5% which is our target tolerance for a practical application.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128702584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN 一个256点数据流调度2×2 MIMO FFT/IFFT处理器用于IEEE 802.16无线城域网
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708789
Fang-Li Yuan, Yi-Hsien Lin, Chih-Feng Wu, M. Shiue, Chorng-Kuang Wang
{"title":"A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN","authors":"Fang-Li Yuan, Yi-Hsien Lin, Chih-Feng Wu, M. Shiue, Chorng-Kuang Wang","doi":"10.1109/ASSCC.2008.4708789","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708789","url":null,"abstract":"In this paper, an efficient solution of MIMO FFT/IFFT processor for IEEE 802.16 WMAN is presented. By applying the proposed mixed-radix dataflow scheduling (MRDS) technique, the effective hardware utilization can be raised to 100%. Therefore, a single butterfly unit within each pipeline stage is sufficient to deal with the two data sequences, and the hardware complexity is significantly reduced. The proposed FFT/IFFT processor has been emulated on the FPGA board. The signal-to-quantization noise ratio (SQNR) is over 44 dB for QPSK and 16/64-QAM signals. Furthermore, a test chip has been designed using standard 0.18-mum CMOS technology with a core area of 887 times 842 mum2. According to the post-layout simulation results, the design consumes 46 mW at 64 MHz operating frequency, which meets the maximum throughput requirements of IEEE 802.16 WMAN.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128733191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A continuous time ΔΣ ADC with clock timing calibration 一个带时钟定时校准的连续时间ΔΣ ADC
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708804
Jen-Che Tsai, Jhy-Rong Chen, K. Hsueh, Mumei Chen
{"title":"A continuous time ΔΣ ADC with clock timing calibration","authors":"Jen-Che Tsai, Jhy-Rong Chen, K. Hsueh, Mumei Chen","doi":"10.1109/ASSCC.2008.4708804","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708804","url":null,"abstract":"A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requirement of the adder for excess loop delay compensation. The ADC has been designed and fabricated in a 0.13 um CMOS process. The ADC achieves 75 dB dynamic range and 69 dB peak signal-to-noise ratio (SNR) at 1 MHz signal bandwidth and 64 MHz sampling rate while dissipating 2.2 mW from 1.2 V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117089144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dual-section-average (DSA) analog-to-digital converter (ADC) in digital pulse width modulation (DPWM) DC-DC converter for reducing the problem of limiting cycle 双段平均(DSA)模数转换器(ADC)中的数字脉宽调制(DPWM) DC-DC转换器用于减少限环问题
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708749
Yu-Chi Huang, Hsin-Chao Chen, Tin-Jong Tai, Ke-Horng Chen
{"title":"Dual-section-average (DSA) analog-to-digital converter (ADC) in digital pulse width modulation (DPWM) DC-DC converter for reducing the problem of limiting cycle","authors":"Yu-Chi Huang, Hsin-Chao Chen, Tin-Jong Tai, Ke-Horng Chen","doi":"10.1109/ASSCC.2008.4708749","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708749","url":null,"abstract":"This paper proposes a dual-section average (DSA) analog-to-digital converter (ADC) to achieve a closed-loop digital pulse width modulation (DPWM) DC-DC converter with performance compatible to that by the analog PWM converter. For a 2.4 V input voltage, a regulated output voltage of 1.2 V can provide output current of 600 mA without any off-chip compensators. Besides, the output ripple can be reduced to about 8 mVp-p by theoretical result. The test chip was fabricated in 0.35 mum CMOS technology. Owing to the parasitic resistance, the output ripple of the experimental result is within 8 mVp-p. Furthermore, the transient recovery time is within 50 mus when load current changes from 120 mA to 600 mA, or vice versa.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114799343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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