A 16Gb/s 65nm CMOS transceiver for a memory interface

Abstract

A transceiver for a memory controller operating at 16 Gb/s per link is implemented in 65 nm CMOS process. Timing calibration, equalization and diagnostic circuits for both memory read and write are on the controller to optimize the overall system performance and cost. A 5-tap TX FIR and a continuous time RX equalizer with active inductor loads are employed. The transceiver also includes a diagnostic circuit which can add a programmable DC differential voltage offset and produce actual eye diagrams for both write and read links. It is demonstrated that each link can operate at 16 Gb/s with a timing margin of 0.19 UI at a BER of 10-12.