{"title":"一个带时钟定时校准的连续时间ΔΣ ADC","authors":"Jen-Che Tsai, Jhy-Rong Chen, K. Hsueh, Mumei Chen","doi":"10.1109/ASSCC.2008.4708804","DOIUrl":null,"url":null,"abstract":"A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requirement of the adder for excess loop delay compensation. The ADC has been designed and fabricated in a 0.13 um CMOS process. The ADC achieves 75 dB dynamic range and 69 dB peak signal-to-noise ratio (SNR) at 1 MHz signal bandwidth and 64 MHz sampling rate while dissipating 2.2 mW from 1.2 V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A continuous time ΔΣ ADC with clock timing calibration\",\"authors\":\"Jen-Che Tsai, Jhy-Rong Chen, K. Hsueh, Mumei Chen\",\"doi\":\"10.1109/ASSCC.2008.4708804\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requirement of the adder for excess loop delay compensation. The ADC has been designed and fabricated in a 0.13 um CMOS process. The ADC achieves 75 dB dynamic range and 69 dB peak signal-to-noise ratio (SNR) at 1 MHz signal bandwidth and 64 MHz sampling rate while dissipating 2.2 mW from 1.2 V supply.\",\"PeriodicalId\":143173,\"journal\":{\"name\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2008.4708804\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708804","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A continuous time ΔΣ ADC with clock timing calibration
A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requirement of the adder for excess loop delay compensation. The ADC has been designed and fabricated in a 0.13 um CMOS process. The ADC achieves 75 dB dynamic range and 69 dB peak signal-to-noise ratio (SNR) at 1 MHz signal bandwidth and 64 MHz sampling rate while dissipating 2.2 mW from 1.2 V supply.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
