A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN

Fang-Li Yuan, Yi-Hsien Lin, Chih-Feng Wu, M. Shiue, Chorng-Kuang Wang
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引用次数: 14

Abstract

In this paper, an efficient solution of MIMO FFT/IFFT processor for IEEE 802.16 WMAN is presented. By applying the proposed mixed-radix dataflow scheduling (MRDS) technique, the effective hardware utilization can be raised to 100%. Therefore, a single butterfly unit within each pipeline stage is sufficient to deal with the two data sequences, and the hardware complexity is significantly reduced. The proposed FFT/IFFT processor has been emulated on the FPGA board. The signal-to-quantization noise ratio (SQNR) is over 44 dB for QPSK and 16/64-QAM signals. Furthermore, a test chip has been designed using standard 0.18-mum CMOS technology with a core area of 887 times 842 mum2. According to the post-layout simulation results, the design consumes 46 mW at 64 MHz operating frequency, which meets the maximum throughput requirements of IEEE 802.16 WMAN.
一个256点数据流调度2×2 MIMO FFT/IFFT处理器用于IEEE 802.16无线城域网
本文提出了ieee802.16无线城域网中MIMO FFT/IFFT处理器的高效解决方案。采用混合基数数据流调度(MRDS)技术,可以将有效的硬件利用率提高到100%。因此,每个管道级内的单个蝶形单元足以处理两个数据序列,并且大大降低了硬件复杂性。所提出的FFT/IFFT处理器已经在FPGA板上进行了仿真。QPSK和16/64-QAM信号的信量化噪声比(SQNR)均大于44 dB。此外,采用标准的0.18 μ m CMOS技术,设计了核心面积为887 × 842 μ m的测试芯片。布局后仿真结果表明,该设计在64mhz工作频率下功耗为46mw,满足IEEE 802.16 WMAN的最大吞吐量要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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