2019 IEEE Applied Power Electronics Conference and Exposition (APEC)最新文献_第8页

A Model Predictive Voltage Control using Virtual Space Vectors for Grid-Forming Energy Storage Converters 基于虚拟空间矢量的并网储能变换器模型预测电压控制

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722151

W. Alhosaini, Yue Zhao

引用次数: 2

Two-Phase Interleaved Resonant Switched-Capacitor DC-DC Converter with Coupled Inductors and Custom LC Resonator 带耦合电感和定制LC谐振器的两相交错谐振开关电容DC-DC变换器

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722111

Prescott H. McLaughlin, Phyo Aung Kyaw, M. Kiani, C. Sullivan, J. Stauth

引用次数: 7

Simple Fully Analytical Copper Loss Model of Litz Wire Made of Strands Twisted in Multiple Levels 多层绞合的Litz线铜损的简单全解析模型

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721827

K. Umetani, J. Acero, H. Sarnago, Óscar Lucía, E. Hiraki

{"title":"Simple Fully Analytical Copper Loss Model of Litz Wire Made of Strands Twisted in Multiple Levels","authors":"K. Umetani, J. Acero, H. Sarnago, Óscar Lucía, E. Hiraki","doi":"10.1109/APEC.2019.8721827","DOIUrl":"https://doi.org/10.1109/APEC.2019.8721827","url":null,"abstract":"The Litz wire has been widely utilized as a wire with a low copper loss under high-frequency operation. However, design optimization of the Litz wire is difficult because this wire generally has a complicated structure of thin strands twisted in multiple levels, which hinders both of the analytical and numerical prediction of the copper loss. To overcome this issue, recent studies have proposed the analytical models of the copper loss in the bundle of twisted strands, which is the basic components constituting the Litz wire. This paper constructs a simple analytical copper loss model of the Litz wire based on these preceding insights. In addition to these insights, the proposed model further considers the effect of the inclination angle of the strands to the Litz wire on the proximity effect loss. The proposed model was tested in comparison with the experimentally measured AC resistance of commercially available Litz wires. As a result, the predicted AC resistance showed good agreement with the measured ac resistance, suggesting the effectiveness of the proposed model.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132070605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Enhancing Inherent Flux Balancing in a Dual-Active Bridge Using Adaptive Modulation 利用自适应调制增强双有源电桥的固有磁通平衡

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722054

C. Winter, J. Riedel, Z. Mohzani, Raphael Mencher, S. Butzmann

引用次数: 3

Series diode balancing and diode evaluation for high-voltage high-frequency power converters 高压高频功率变换器的串联二极管平衡与二极管评估

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721875

Yiou He, D. Perreault

引用次数: 2

A Hybrid PWM Modulation for EMI Filter Size Reduction in a 10 kW GaN-Based Three Phase Inverter 混合PWM调制在10kw gan型三相逆变器中减小EMI滤波器尺寸

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722047

Yousef Abdullah, Will Perdikakis, He Li, Ke Wang, Yue Zhang, Xiaodan Wang, Jin Wang, Liming Liu, S. Bala

引用次数: 5

Design and optimization of a wide dynamic range Programmable Power Supply for data center applications 用于数据中心应用的大动态范围可编程电源的设计与优化

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722072

R. Christen, J. Smajic, A. Sridhar, T. Brunschwiler

{"title":"Design and optimization of a wide dynamic range Programmable Power Supply for data center applications","authors":"R. Christen, J. Smajic, A. Sridhar, T. Brunschwiler","doi":"10.1109/APEC.2019.8722072","DOIUrl":"https://doi.org/10.1109/APEC.2019.8722072","url":null,"abstract":"A point-of-load (PoL) voltage regulator module (VRM) with high efficiency, conversion ratio and power density can enable dense integration of CPUs in data centers, and subsequently increase the overall data center energy efficiency. State-of-the-art VRMs are already quite small and achieve high peak efficiencies. However, given the variable nominal load currents of these VRMs in response to changing computational loads of the data centers, a flat high-efficiency response is more desirable. This paper presents a programmable VRM with a flat < 90 % efficiency response over a wide load dynamic range. The proposed programmable VRM is based on multiphase interleaved synchronous buck topology with phase shedding. An extensive exploration of different power switch technologies has been performed in order to obtain the most suitable MOSFET technology for this topology. Our design space exploration also included sweeping the voltage conversion ratio, passive components and switching frequency. The finalized programmable VRM, using discrete Si-MOSFETs, performs a 12–1 V DC-DC conversion with an operating load range of 10 – 200 A and a switching frequency of 200 kHz. Experimental characterization of the VRM demonstrates an efficiency of 92.2 % across the wide load range of 10 – 200 A, confirming design simulations with a maximum relative error of 0.7 %.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"16 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Modular Multilevel Converter with Self Voltage Balancing 具有自平衡电压的模块化多电平变换器

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721876

Yunting Liu, F. Peng

{"title":"A Modular Multilevel Converter with Self Voltage Balancing","authors":"Yunting Liu, F. Peng","doi":"10.1109/APEC.2019.8721876","DOIUrl":"https://doi.org/10.1109/APEC.2019.8721876","url":null,"abstract":"The modular feature of modular multilevel converter (MMC) distinguishes itself from other topologies for medium-/high-voltage applications. However, as the count of sub-modules increases, the control complexity of voltage balancing for each sub-module sharply increases. Conventionally, the MMC is deemed to have no inherit voltage balancing property without voltage monitoring and control. This paper mathematically proves that MMC capacitor voltage is self-balanced by nature. This implies that MMC could achieve the sub-module capacitor voltage balancing without any monitoring or control. Based on the mathematical proof, a novel modulation, namely Y-Matrix Modulation (YMM), is proposed to transform the math analysis into modulation practice. With the proposed YMM, MMCs are secured self voltage balancing. Conventionally, either a complicated voltage balancing control, or extra components must be embedded to MMC to balance the capacitor voltage. Compared to conventional MMC capacitor voltage balancing strategies, YMM features extremely simple algorithms and good reachability to high-level MMCs while maintaining the original half-bridge sub-module topology.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121762863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Switching Sequence Synthesis for Minimizing RMS Current in a Single-Inductor-Multi-Output Converter 在单电感-多输出变换器中最小有效值电流的开关序列合成

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722226

S. Maji, K. Hariharan, S. Kapat

{"title":"Switching Sequence Synthesis for Minimizing RMS Current in a Single-Inductor-Multi-Output Converter","authors":"S. Maji, K. Hariharan, S. Kapat","doi":"10.1109/APEC.2019.8722226","DOIUrl":"https://doi.org/10.1109/APEC.2019.8722226","url":null,"abstract":"Single-inductor-multiple-output (SIMO) DC-DC converters offer a compact power management solution in low power applications for simultaneously powering multiple DC loads. While using a time-interleaved PWM control technique, there exist multiple feasible switching sequences in a SIMO converter. The primary research focus in the recent past remains in minimizing the cross regulation and coupling effects. However, there has been a little emphasis on the design of the switching sequence for minimizing the RMS inductor current in order to minimize the conduction losses. This paper is aimed in finding a suitable switching sequence for the reduction in the RMS value of the inductor current iL in a SIMO converter. The primary objectives are to (i) find the practically feasible switching sequences, (ii) identify the sequence with the lowest RMS value of iL at a given operating condition, and (iii) develop an optimal algorithm for dynamically varying operating conditions. A prototype of dual-output buck converter is made. A three-output simulated and a two-output experimental case studies are considered, and analytical predictions are found to be consistent with the results.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116604218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dynamic Bus Voltage Configuration in a Two-Stage Multi-Phase Buck Converter to Mitigate Transients 两级多相降压变换器的动态母线电压配置以减轻瞬变

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722175

Arnab Acharya, V. I. Kumar, S. Kapat

{"title":"Dynamic Bus Voltage Configuration in a Two-Stage Multi-Phase Buck Converter to Mitigate Transients","authors":"Arnab Acharya, V. I. Kumar, S. Kapat","doi":"10.1109/APEC.2019.8722175","DOIUrl":"https://doi.org/10.1109/APEC.2019.8722175","url":null,"abstract":"This paper proposes a dynamic bus voltage transition technique in a two-stage multi-phase buck converter for 48 V to point-of-load (PoL) applications. The proposed topology uses a bank of pre-charged switching capacitors at the output of the first-stage buck converter. This configuration helps to achieve an immediate intermediate bus voltage transition while supplying a (second-stage) multi-phase buck converter. This can substantially speed-up a large-signal transient recovery by adjusting the bus voltage to its highest voltage level. Thereafter, near steady-state, the bus voltage is set to its (lower) optimum value for improving the overall efficiency and also for ripple cancellation for the second-stage converter. A higher bus voltage helps in proportionally reducing the output capacitance for the second-stage while retaining the (voltage) undershoot within the desired limit. This helps to reduce recovery time and current overshoot during a step-reference transient. A hardware prototype of the proposed architecture is made, and improved performance is demonstrated using simulation and experimental results.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115147591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3