{"title":"Dynamic Bus Voltage Configuration in a Two-Stage Multi-Phase Buck Converter to Mitigate Transients","authors":"Arnab Acharya, V. I. Kumar, S. Kapat","doi":"10.1109/APEC.2019.8722175","DOIUrl":null,"url":null,"abstract":"This paper proposes a dynamic bus voltage transition technique in a two-stage multi-phase buck converter for 48 V to point-of-load (PoL) applications. The proposed topology uses a bank of pre-charged switching capacitors at the output of the first-stage buck converter. This configuration helps to achieve an immediate intermediate bus voltage transition while supplying a (second-stage) multi-phase buck converter. This can substantially speed-up a large-signal transient recovery by adjusting the bus voltage to its highest voltage level. Thereafter, near steady-state, the bus voltage is set to its (lower) optimum value for improving the overall efficiency and also for ripple cancellation for the second-stage converter. A higher bus voltage helps in proportionally reducing the output capacitance for the second-stage while retaining the (voltage) undershoot within the desired limit. This helps to reduce recovery time and current overshoot during a step-reference transient. A hardware prototype of the proposed architecture is made, and improved performance is demonstrated using simulation and experimental results.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APEC.2019.8722175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper proposes a dynamic bus voltage transition technique in a two-stage multi-phase buck converter for 48 V to point-of-load (PoL) applications. The proposed topology uses a bank of pre-charged switching capacitors at the output of the first-stage buck converter. This configuration helps to achieve an immediate intermediate bus voltage transition while supplying a (second-stage) multi-phase buck converter. This can substantially speed-up a large-signal transient recovery by adjusting the bus voltage to its highest voltage level. Thereafter, near steady-state, the bus voltage is set to its (lower) optimum value for improving the overall efficiency and also for ripple cancellation for the second-stage converter. A higher bus voltage helps in proportionally reducing the output capacitance for the second-stage while retaining the (voltage) undershoot within the desired limit. This helps to reduce recovery time and current overshoot during a step-reference transient. A hardware prototype of the proposed architecture is made, and improved performance is demonstrated using simulation and experimental results.