2019 IEEE Applied Power Electronics Conference and Exposition (APEC)最新文献_第7页

Highly Efficient EV Battery Charger Using Fractional Charging Concept with SiC Devices 基于SiC器件的分式充电概念的高效电动汽车电池充电器

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722191

T. Kanstad, Morten Birkerod Lillholm, Zhe Zhang

引用次数: 18

Harmonic Transfer-Function Model of Three-Phase Synchronous Reference Frame PLL under Unbalanced Grid Conditions 不平衡电网条件下三相同步参考框架锁相环谐波传递函数模型

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721842

Y. Liao, Xiongfei Wang, Xiaolong Yue, Hong Gong

引用次数: 5

A Fast Transient Flip Voltage Follower Based Low Dropout Regulator with AC-Coupled Pseudo Tri-Loop Technique Without Using Any Output Capacitor 基于交流耦合伪三环技术的快速瞬态翻转电压从动器低压差稳压器，不使用任何输出电容

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722137

Tzu-Hao Chien, Ching-Jan Chen, S. Li, Chieh-Ju Tsai

{"title":"A Fast Transient Flip Voltage Follower Based Low Dropout Regulator with AC-Coupled Pseudo Tri-Loop Technique Without Using Any Output Capacitor","authors":"Tzu-Hao Chien, Ching-Jan Chen, S. Li, Chieh-Ju Tsai","doi":"10.1109/APEC.2019.8722137","DOIUrl":"https://doi.org/10.1109/APEC.2019.8722137","url":null,"abstract":"This paper presents a fast transient low-dropout regulator (LDO) without using any output capacitor for system-on-chip (SoC) powering. Conventional LDO needs a pF to nF level output capacitor for transient voltage drop suppression and encounters stability issue in light load condition. The proposed tri-loop architecture includes a flip-voltage-follower (FVF) stage, an ac-coupled capacitor, and an error amplifier, which resolves the stability issue at different load condition without any output capacitor. The ac-coupled capacitor which forms an ac-coupled loop shortens the response time. The error amplifier (EA) regulates output voltage accurately with high DC gain. The proposed LDO is implemented into an integrated circuit (IC) using 0.18um CMOS process. The whole chip area is 0.398mm2, and the LDO only occupies 0.094mm2. The full transistor-level simulation results demonstrate that undershoot and overshoot voltage are only 270mV and 272mV respectively for load transient of 1-20mA within slew rate of 20mA/100ps. The FVF-based LDO with the proposed technique achieves a response time of 0.225ns, which reaches figure-of-merit (FOM) of 0.388ps.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"116 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114109022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Simplified Optimal Trajectory Control for 1 MHz LLC Converter with Wide Input Voltage Range 宽输入电压范围1mhz LLC变换器的简化最优轨迹控制

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722275

Ahmed Nabih, M. Ahmed, Qiang Li, F. Lee

引用次数: 9

A Simple Analytical Technique for Evaluating the 2-D Conductive Losses in Isolated Rectangular Conductor 一种评估孤立矩形导体二维导电损耗的简单分析技术

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722123

Xiaohui Wang, Li Wang, Ling Mao, Yaojia Zhang

引用次数: 1

A Pareto-Optimized, Capacitively Isolated SEPIC Converter for Wide Load Ranges and High Frequency Power Conversion 用于宽负载范围和高频功率转换的帕累托优化电容隔离SEPIC转换器

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721997

D. Bura, T. Plum, R. D. De Doncker

引用次数: 1

Small-Signal Phasor Modeling of an Underwater IPT System in Constant Current Distribution 恒流分布水下IPT系统的小信号相量建模

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8721899

Anindya Chitta Bagchi, Hongjie Wang, T. Saha, R. Zane

引用次数: 3

Pulse Energy Modulation for a Single-Phase Bridge Inverter with Power Decoupling Capability 具有功率去耦能力的单相桥式逆变器脉冲能量调制

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722132

Shuang Xu, Liuchen Chang, Riming Shao

引用次数: 0

A Transformer-Less Quadruple Active Half-Bridge Converter for the Two-Stage 48V VRM Application 用于两级48V VRM的无变压器四重有源半桥变换器

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722255

Somnath Khatua, D. Kastha, S. Kapat

{"title":"A Transformer-Less Quadruple Active Half-Bridge Converter for the Two-Stage 48V VRM Application","authors":"Somnath Khatua, D. Kastha, S. Kapat","doi":"10.1109/APEC.2019.8722255","DOIUrl":"https://doi.org/10.1109/APEC.2019.8722255","url":null,"abstract":"A high power density transformer-less quadruple active half-bridge DC-DC converter suitable for the input-stage of a two-stage 48 V VRM is proposed in this paper. The converter consists of four half-bridge circuits and three small AC link power transfer inductors connected strategically among them. In the absence of the transformer, the voltage matching among the half-bridge circuits is achieved by stacking all of them together in series. The converter achieves high efficiency since all of its switches undergo inherent zero-voltage switching. It also needs to handle reduced power as a significant portion of the total load power flows directly to the output. It has several other advantages like reduced switch voltage and current stresses, efficient voltage regulation ability (and hence scalability), and a wide range variable switching frequency operation. These features allow the converter to achieve a flat high-efficiency curve. Topological evolution of the converter from its isolated version is explained and the concept is generalised to obtain the transformer-less multiple active half-bridge converters. Thereafter, the circuit operation of the quadruple active half-bridge configuration is analysed and a capacitor voltage control scheme is proposed. Finally, experimental results from a 48 V-12 V, 8 A laboratory prototype show that the converter achieves a peak efficiency of 98.1% and a full load efficiency of 97.23%.","PeriodicalId":142409,"journal":{"name":"2019 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127278390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

An Improved High Voltage DC-DC Converter with Partial-Resonant Network for Enhanced Efficiency and Power Density in Electric Vehicle Applications 一种改进的部分谐振网络高压DC-DC变换器，用于提高电动汽车的效率和功率密度

2019 IEEE Applied Power Electronics Conference and Exposition (APEC) Pub Date : 2019-03-17 DOI: 10.1109/APEC.2019.8722236

Jaehyung Lee, Tae-Won Noh, Jung-Hoon Ahn, Byoung-Kuk Lee

引用次数: 2