2014 IEEE Dallas Circuits and Systems Conference (DCAS)最新文献_第3页

Study on the effectiveness of a Weighted Pseudo Linear approach to emitter localization 加权伪线性方法对发射极定位的有效性研究

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965340

Joshua Stone, Willis Troy, M. Thompson

引用次数: 0

Resonant coupling analysis for a two-coil wireless power transfer system 双线圈无线电力传输系统的谐振耦合分析

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965345

R. Jay, S. Palermo

引用次数: 12

Radix-2h online floating point multipliers 基数-2h在线浮点乘法器

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965332

G. Joseph, R. Devanathan

引用次数: 3

Energy-efficient imprecise reconfigurable computing through probabilistic domain transformation 基于概率域变换的节能非精确可重构计算

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965329

Mohammed Alawad, Mingjie Lin

{"title":"Energy-efficient imprecise reconfigurable computing through probabilistic domain transformation","authors":"Mohammed Alawad, Mingjie Lin","doi":"10.1109/DCAS.2014.6965329","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965329","url":null,"abstract":"Many DSP applications naturally possess so-called “inherent error resilience”, meaning certain degrees of computational errors would not noticeably impair their eventual quality of results. Such a phenomenon offers an interesting opportunity to significantly improve the overall energy efficiency of these DSP applications at the cost of minute degradations in computing accuracy. This work presents a probabilistic-based methodology to perform high-performance DSP applications while achieving low power consumption. Deviating from all published approximate computing methods, our solution leverages a fundamental probability principle to implement a reconfigurable finite impulse response FIR digital filter specifically designed for FPGA-based image and video processors. Our method is trading off performance efficiency and power consumption against accuracy of the output results. To validate this proposed probabilistic architecture for discrete FIR filter, We have developed a 16-tap FIR filter with Virtex 5 FPGA devices (XC5VSX95T-1FF1136). Our prototype of probabilistic-based reconfigurable FIR filter consumes 9 times less power than multiplier-based FIR filter and dissipates 43.13 μJ in dynamic energy consumption to perform filtering on a (256×256) pixel image. We believe that this new architecture can be exploited in all the real-time applications in which energy-efficient FIR filters are required and it can be realized with many other FPGA device families.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128272508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Predicting ADC: A new approach for low power ADC design 预测ADC:低功耗ADC设计的新方法

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965323

Nicholas Wood, Nan Sun

引用次数: 14

28 nm Charge sensitive preamplifier using 1 GΩ dual PMOS feedback resistor operating in the weak inversion region 28纳米电荷敏感前置放大器，采用1个GΩ双PMOS反馈电阻，工作在弱反转区

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965318

Mahmoud Hassan, Hazem W. Marar

引用次数: 0

Variation resilient high performance and low voltage single ended sense amplifier 可变弹性高性能低电压单端感测放大器

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965324

R. S. Rao, Shahid Ali

{"title":"Variation resilient high performance and low voltage single ended sense amplifier","authors":"R. S. Rao, Shahid Ali","doi":"10.1109/DCAS.2014.6965324","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965324","url":null,"abstract":"Sense Amplifier is an essential component in an embedded memory. Multiple voltage mode sensing techniques have been developed for embedded SRAMs where differential on bitlines is sensed and amplified to read the data from SRAM bitcell. Unlike SRAMs, embedded CMOS Read Only Memories (ROMs) have unique challenges. ROM cell is typically a single NMOS transistor and hence differential voltage is not available for ROM bit sensing. For area efficiency, a large number of bitcells is stitched on the bitline. This creates an additional bottleneck for ROM sensing where sense amplifier has to sense the data correctly for the least Ion (`ON' current of a transistor) and for the maximum Ioff (`OFF' current of transistors on a bitline). Process variation, device mismatch and temperature adversely affect Ion to Ioff ratio imposing further constraint to ROM sensing. Additionally, large bitline capacitance limits the ROM performance. As ROM bitline pitch is extremely limited, sense amplifier has to fit into the restricted layout area. Low Voltage operation adds to the list of challenges. Novel Sense Amplifier techniques need to address these challenges. This paper describes sensing techniques to overcome ROM specific problems; Supplemented Inverter based Sense Amplifier (SISA) has been introduced and compared against Diode Mirrored Resistive Sense Amplifier (DMRS). SISA is implemented in 28nm Low Power process node. This sense amplifier is proven in Silicon and works across splits down up to 0.7v. 2ns access time is achieved for 1Mb instance. SISA is also proven in multiple other ultra-low power technology nodes.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129678452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A loop-breaking method for simulation of feedback circuits using a VCVS-terminated subnetwork model 一种用vcvs终止子网络模型模拟反馈电路的破环方法

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965317

H. T. Russell, R. Carter, W. Davis

引用次数: 0

Enhancement in IEEE 1500 standard for at-speed test and debug IEEE 1500标准中高速测试和调试的改进

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965327

Ghazanfar Ali, F. Hussin, N. B. Z. Zain Ali, N. H. Hamid, R. Adnan

引用次数: 0

Real-time active noise control of multi-tones and MRI acoustic noise in fMRI bore with signal decomposition and parallel hybrid RLS-NLMS adaptive algorithms 基于信号分解和并行混合RLS-NLMS自适应算法的fMRI多音和MRI噪声实时主动控制

2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965339

Sri Hari Krishna Vemuri, Anshuman Ganguly, I. Panahi

引用次数: 3