Predicting ADC: A new approach for low power ADC design

Abstract

In this paper we present a scaling friendly supplement to ADC designs which can produce increases in conversion speed and power efficiency by attempting to predict the value of the next sample. To accomplish this we use a first order difference equation to predict the values of several of the bits in the next sample. In doing so, we can save power by reducing the number of comparisons and by reducing the capacitor array switching power.