{"title":"Techniques for dynamic range enhancement in a frequency-folded broadband channelizer","authors":"Wei-Gi Ho, V. Singh, Travis Forbes, R. Gharpurey","doi":"10.1109/DCAS.2014.6965349","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965349","url":null,"abstract":"Recent work in spectrum-channelizing receivers has demonstrated the ability to simultaneously detect and down-convert broadband inputs while using a single LO. This addresses a key design challenge in mixer-bank based spectrum channelizers, namely the requirement for multiple concurrently operating frequency-synthesizers. An approach that simultaneously addresses channelization and digitization is the frequency-folded analog-to-digital converter. In this work, the use of feedforward and feedback for linearizing such architectures, by combining them with frequency-synthesis capable harmonic-rejection mixers is proposed. Feedforward-based approaches are effective in relaxing the dynamic range requirement of the sub-ADCs used at baseband, while feedback-based approaches are useful for relaxing dynamic range at the input of the channelizer.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127160716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Emeretlis, Vasilios I. Kelefouras, G. Theodoridis, G. Glentis
{"title":"Efficient FPGA implementations of volterra DFES for optical systems","authors":"A. Emeretlis, Vasilios I. Kelefouras, G. Theodoridis, G. Glentis","doi":"10.1109/DCAS.2014.6965328","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965328","url":null,"abstract":"In this work suitable architectures and high-throughput FPGA implementations of Volterra Decision Feedback Equalizers (VDFEs) for optical communication links are presented. Two VDFE configurations were selected based on the available resources of the employed FPGA devices, and two multiplexer-based architectures were developed for each of them in order to achieve the target throughput. The comparison of the experimental results with respect to different VDFE configurations, throughput, and FPGA devices points out the platform-specific design characteristics. The introduced architectures meet the desired 10Gb/s throughput, so it is demonstrated that the FPGA is a suitable platform for high-speed optical fiber communication systems.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123666541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On I/Q imbalance effects in full-duplex OFDM decode-and-forward relays","authors":"M. Mokhtar, N. Al-Dhahir, R. Hamila","doi":"10.1109/DCAS.2014.6965343","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965343","url":null,"abstract":"We analyze the outage probability of dual-hop full-duplex decode-and-forward relaying for an orthogonal frequency division multiplexing system in the presence of I/Q imbalance. We derive accurate analytical approximations which quantify the outage probability's functional dependence on the I/Q imbalance level and the residual loopback self-interference average power level. In addition, we derive the condition at which direct transmission outperforms full-duplex decode-and-forward relay-assisted transmission in the presence of I/Q imbalance. Finally, our numerical results confirm the accuracy of our analysis.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121596698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Signal conditioning for polar all-digital OFDM wireless transmitters","authors":"Suhas Illath Veetil, M. Helaoui","doi":"10.1109/DCAS.2014.6965347","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965347","url":null,"abstract":"A novel scheme for conditioning OFDM modulated signals is proposed to facilitate the implementation of mixerless all-digital transmitter using polar RF Digital to Analog Converters (RFDACs). The signal conditioning is applied to the OFDM signal to avoid phase discontinuities, thus mitigating the effects of bandwidth expansion in polar decomposition. The absence of mixers and filters offers wide RF bandwidth and takes the design a step closer to reconfigurable transmitter. To validate this concept, the signal conditioning is applied to an LTE signal and sent to a phase modulator circuit. The performance of the phase modulator in terms of signal quality is assessed using Normalized Mean Square Error (NMSE) metric. It is concluded that the signal conditioning results in a signal that may not comply with the existing standards, but is spectrally efficient and thus enables the use of polar architectures for wideband signals.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134351641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wireless battery charge management for implantable pressure sensor","authors":"S. Majerus, S. Garverick, M. Damaser","doi":"10.1109/DCAS.2014.6965336","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965336","url":null,"abstract":"Implantable medical devices intended for chronic application in deep bodily organs must balance small size with battery capacity. Wireless battery recharge of implanted sensors is a viable option to reduce implant size while removing the physical and regulatory hindrance of continuous RF powering. This paper presents wireless battery recharge circuitry developed for an implantable pressure sensor. The circuits include an RF/DC rectifier, voltage limiter, and constant-current battery charger with 150-mV end-of-charge hysteresis. An AM demodulator drawing zero DC current allows for transmission of commands on the recharge carrier. Reception of a time- and value-coded shutdown command places the implantable system into a 15 nanoampere standby mode. The system can be wirelessly activated from standby by reactivating the external wireless recharge carrier. Test results of the wireless system showed a standby current of 15-nA such that the implant standby time is limited by battery self-discharge. Wireless recharge tests confirmed that a constant recharge rate of 200 μA could be sustained at implant depths up to 20 cm, but with low power transfer efficiency <; 0.1% due to small implant coil size. Battery charge measurements confirmed that daily 4-hour recharge periods maintained the implant state of charge and this recharging could occur during periods of natural patient rest.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121370737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 14-b, 0.1ps resolution coarse-fine time-to-digital converter in 45 nm CMOS","authors":"Huihua Huang, C. Sechen","doi":"10.1109/DCAS.2014.6965319","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965319","url":null,"abstract":"A 14-b, 0.1ps resolution interpolating coarse - fine Time-to-Digital Converter (TDC) has been developed in 45nm CMOS technology. It is based on an asynchronous buffer delay line and an RC delay line. A lookup-table (LUT) based calibration scheme was developed to correct non-linearities due to PVT variations.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130357469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-HMM classification for hand gesture recognition using two differing modality sensors","authors":"Kui Liu, Cheng Chen, R. Jafari, N. Kehtarnavaz","doi":"10.1109/DCAS.2014.6965338","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965338","url":null,"abstract":"This paper presents a multi-Hidden Markov Model (HMM) classification approach for hand gesture recognition by utilizing two differing modality and low-cost sensors. The sensors consist of a Kinect depth camera and a wearable inertial sensor. It is shown that the multi-HMM classification based on nine signals that are simultaneously captured by these two sensors leads to a more robust recognition compared to the situation when only a single HMM classification is used to generate the likelihood probabilities of hand gestures. This approach is applied to the hand gestures of the $1Unistroke Recognizer application and the results obtained indicate a 7% improvement in the overall classification rate over a single HMM classification under realistic conditions.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132116041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Minimum energy operation using robust asynchronous logic with sleep transistors","authors":"Akshay Sridharan, C. Sechen","doi":"10.1109/DCAS.2014.6965334","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965334","url":null,"abstract":"We demonstrate minimum energy operation using a robust approach to asynchronous logic design combined with the use of sleep transistors. The combined approach yields extremely low power and energy for a system operating in the subthreshold regime. This enables operation at voltages below those associated with the previously proposed minimum energy operating point (MEP) and therefore appreciably reduces the energy consumption compared to MEP. We also demonstrate that the robustness of our asynchronous system under Monte Carlo variations can actually yield significant additional power savings compared to a synchronous design.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129274175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of a low-complexity low-latency arbitrary resampler on GPUs","authors":"S. C. Kim, S. Bhattacharyya","doi":"10.1109/DCAS.2014.6965333","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965333","url":null,"abstract":"Modern communication systems have data rates and sampling rates that are tightly coupled. Resampling is necessary in order to convert to some desired sampling rate, which is usually a multiple of the data rate. The resampling process is an integral part of transceiver systems and must be designed accurately and carefully. In this paper, we present a low complexity and low latency arbitrary resampling method based on graphics processing units (GPUs). Our proposed flexible and all-software-based resampling method requires no precomputation of filters and yet yields high performance by taking advantage of unique features found in GPUs.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121289409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CMOS inverter-based voltage and current references in short channel technologies","authors":"K. Raghunandan, T. R. Viswanathan","doi":"10.1109/DCAS.2014.6965322","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965322","url":null,"abstract":"This paper presents the design of voltage and current references in short channel CMOS technologies operating with Low Supply Voltages (<; 1.2V). The objective is to design simple circuits having good Power Supply Rejection (PSR) with minimal power consumption and area which are easy to re-use. The references are based on class AB CMOS inverters and current mirrors. A voltage reference is obtained as a scaled sum of two diode voltages carrying different current densities so that it is equal to a fraction of the bandgap voltage of silicon. The current reference is obtained by calibrating a simple current source using the bandgap voltage and a switched capacitor conductance clocked by the system clock.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123979877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}