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Perils of power prediction in early power-integrity analysis 早期电力完整性分析中电力预测的危险
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965335
A. Arun, Shane Stelmach, R. Venkatasubramanian, Jose Flores, Colin Jitlal, F. Cano
{"title":"Perils of power prediction in early power-integrity analysis","authors":"A. Arun, Shane Stelmach, R. Venkatasubramanian, Jose Flores, Colin Jitlal, F. Cano","doi":"10.1109/DCAS.2014.6965335","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965335","url":null,"abstract":"Early power integrity and peak power analyses for multi-million gate system on chip (SoC) in advanced technology nodes pose significant methodology definition and implementation challenges. Typically in a SoC, processors and other high performance IPs are dominant contributors to peak power and power integrity issues. To get an early look ahead of potential power integrity issues and to estimate peak di/dt issues in the SoC, it is always desired to analyze potential issues early and address before a silicon failure. This paper presents an overview of implementation challenges faced in RTL based power for predictive power analysis and analyzing peak di/dt issues ahead of time in the context of TI C66× DSP core based multicore SoC.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121277814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Volume and concentration identification by using an electrowetting on dielectric device 电介质装置上电润湿法的体积和浓度鉴定
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965350
Yiyan Li, Hongzhong Li, R. J. Baker
{"title":"Volume and concentration identification by using an electrowetting on dielectric device","authors":"Yiyan Li, Hongzhong Li, R. J. Baker","doi":"10.1109/DCAS.2014.6965350","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965350","url":null,"abstract":"An ultra-sensitive electrowetting on dielectric (EWOD) capacitance measurement system is proposed in this study. A 24-bit integrated circuit (IC) capacitance-to-digital (CDC) sensor is used to convert the capacitance changes caused by variations in droplet volume and concentration to digital data. A 2.3 mm by 2.3 mm printed circuit board (PCB) based electrode pair is used to sense the analog capacitance change. The capacitance of pure water and NaCl solutions are tested by the CDC system. Desktop-drawing software is used to fix the position of the droplet to obtain a small capacitance deviation of 10 IF. Result shows the CDC system can resolve the capacitance changes caused by adding 0.1 micro-liter droplets or by increasing the NaCl concentration by 1%. The digital output of the sensor is interface-friendly to microcontrollers.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"21 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120905738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
EMG based classification of percentage of maximum voluntary contraction using artificial neural networks 基于肌电图的最大自主收缩百分比人工神经网络分类
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965337
Stephen Hickman, R. Alba-Flores, M. Ahad
{"title":"EMG based classification of percentage of maximum voluntary contraction using artificial neural networks","authors":"Stephen Hickman, R. Alba-Flores, M. Ahad","doi":"10.1109/DCAS.2014.6965337","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965337","url":null,"abstract":"This paper presents an application of an Artificial Neural Network (ANN) for the classification of Electromyography (EMG) signals. The classification system has been designed to classify the percentage of maximum voluntary contraction (%MVC) from the bicep muscle. The EMG signals used in this study have been generated using a computer muscle model. Three statistical input features are extracted from the EMG signals and different structures of ANNs and training algorithms have been considered in the study. A 16 neuron hidden layer architecture trained with the scaled conjugate gradient algorithm has been found to be more efficient than the other ANN architectures tested in classifying 9 different bicep muscle contraction levels as a unit of %MVC than other ANN architectures. The ultimate goal of this research is to design a robotic system for people with disabilities and the elderly by utilizing muscle contraction levels as the input of tasks for the robot.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127600061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A dual positive feedback three-stage low noise amplifier 双正反馈三级低噪声放大器
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965320
M. Jalalifar, Gyung-Su Byun
{"title":"A dual positive feedback three-stage low noise amplifier","authors":"M. Jalalifar, Gyung-Su Byun","doi":"10.1109/DCAS.2014.6965320","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965320","url":null,"abstract":"A three-stage low noise amplifier (LNA) using dual positive feedback is presented in this paper. In order to increase voltage gain and forward gain, two positive feedbacks are employed in the LNA circuit. Moreover, the LNA transistors operate at a moderate inversion region, so it is suitable to use in an ultra-low voltage receiver. The proposed LNA is simulated in 0.13μm CMOS technology. The results show that the LNA achieves a minimum noise figure of 3.28dB, a 28dB voltage gain, and a 15.8dB forward gain at 7.1GHz. The LNA consumes 0.92mW from a 0.5V power supply.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127612672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-voltage and temperature compensated ring VCO design 低压和温度补偿环压控振荡器设计
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965321
Guoying Wu, Kexu Sun, Shita Guo, Tao Zhang, Tianzuo Xi, Rui Wang, P. Gui
{"title":"A low-voltage and temperature compensated ring VCO design","authors":"Guoying Wu, Kexu Sun, Shita Guo, Tao Zhang, Tianzuo Xi, Rui Wang, P. Gui","doi":"10.1109/DCAS.2014.6965321","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965321","url":null,"abstract":"A low-voltage, two-stage ring voltage-controlled oscillator (VCO) which can tolerate temperature variation is presented in this paper. Designed using a 0.13 μm CMOS technology, this VCO is capable of operating at 1-V power supply voltage not only for low power consumption, but also to reduce hot-carrier effects and improve reliability and lifetime. It incorporates coarse and fine frequency tuning mainly for tolerance of process variations while achieving small control-voltage-to-frequency gain and enough tuning range of the VCO. Most importantly, a new temperature compensation technique which is suitable for low power supply voltage design is proposed to enable continuous operation of the VCO in variable ambient temperatures environment. Simulations show that with the proposed techniques, the VCO can tolerate process variations, dynamically adapt to different temperatures, and achieve a low temperature sensitivity of 34 ppm/°C over the range from -40°C to 120 °C.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131201925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Effect of switchbox topologies and net ordering on 3D FPGA routing 开关盒拓扑和网络排序对三维FPGA路由的影响
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965330
Girish Deshpande, D. Bhatia
{"title":"Effect of switchbox topologies and net ordering on 3D FPGA routing","authors":"Girish Deshpande, D. Bhatia","doi":"10.1109/DCAS.2014.6965330","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965330","url":null,"abstract":"The growing need for smaller form factors of smartphones and other handheld devices with greater computational capabilities has resulted in the emergence of stacked silicon (3D) architectures (also referred to as 2.SD type of devices by industry). The emergence of such devices requires us to re-evaluate existing CAD approaches to placement and routing. The extension of well established place and route tools to stacked (3D) FPGAs poses a new set of challenges. This short preliminary study uses a well known academic tool, TPR (Three-dimensional place and route) to examine the impact of switchbox topologies and net ordering on routing of stacked FPGAs. The results of this study indicate that routing multi-layer nets first yield better overall routing. This study also proposes some future avenues of research that need to be explored to thoroughly understand this problem.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133313021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Digitally intensive wireless transmitter architecture employing RF pulse width modulation 采用射频脉宽调制的数字密集型无线发射机架构
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965346
Hyejeong Song, R. Gharpurey
{"title":"Digitally intensive wireless transmitter architecture employing RF pulse width modulation","authors":"Hyejeong Song, R. Gharpurey","doi":"10.1109/DCAS.2014.6965346","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965346","url":null,"abstract":"A digitally-intensive Cartesian RF transmitter based on three-level pulse width modulation (PWM) is proposed. The architecture utilizes two PLL-based RF-PWM generators to modulate baseband I and Q signals to switching signals at RF, which are used to drive class-D output stages. Due to the use of a ring voltage controlled oscillator (VCO), the architecture is well-suited for multiband operation. A switched capacitor technique is used to provide a differential three-level RF-PWM output. The proposed transmitter is simulated in a 65-nm CMOS process, and achieves a peak output power of 22 dBm with 48% and 33% peak power added efficiency (PAE) at 900 MHz and 1.95 GHz respectively.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116300393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Reducing leakage power in wearable medical devices using memory nap controller 使用记忆小睡控制器降低可穿戴医疗设备的泄漏功率
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965331
O. Olorode, M. Nourani
{"title":"Reducing leakage power in wearable medical devices using memory nap controller","authors":"O. Olorode, M. Nourani","doi":"10.1109/DCAS.2014.6965331","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965331","url":null,"abstract":"The increasing demand for wearable medical devices, coupled with their short battery life, has led to a renewed interest in low power processors. A significant proportion of the total power consumed by these medical device processors, occur in the memory systems, and therefore the focus of sour work. In this paper, we propose a technique that reduces the static power consumption in caches with no side effect on processor perforemance. Our proposed architecture achieves this power saving by deterministically lowering the power state of cache lines that are guaranteed not to be accessed in immediate future cycles. We simulated our architecture across different cache configurations, using widely known CAD tools, and observed up to 92% reduction in static power consumption on SPEC2006 benchmarks with no performance penalties and minimal hardware overhead.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122450633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Zero quiescent current, delay adjustable, power-on-reset circuit 零静态电流，延时可调，通电复位电路
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965326
R. Prakash
{"title":"Zero quiescent current, delay adjustable, power-on-reset circuit","authors":"R. Prakash","doi":"10.1109/DCAS.2014.6965326","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965326","url":null,"abstract":"A power-on-reset (POR) circuit is extremely important in digital and mixed-signal ICs. It is used to initialize critical nodes of digital circuitry inside the chip during power-on. A novel POR circuit having zero quiescent current and an adjustable delay is proposed and demonstrated. The circuit has been designed in 0.5μm CMOS process to work for a supply voltage ranging from 1.8V to 5.5V. The circuit generates a POR signal after a predetermined delay, after the supply voltage crosses a predefined threshold voltage. This delay can be increased or decreased via programmable fuses. The POR threshold does not depend upon the supply ramp rate. The Brown-Out (BO) voltage for the proposed circuit matches the minimum supply voltage required by the digital circuitry inside the IC. The circuit consumes zero steady state current, making it ideal for low power applications.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133454407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Modeling and compensation of antenna RF switching non-idealities in OFDM receivers OFDM接收机天线射频切换非理想性的建模与补偿
2014 IEEE Dallas Circuits and Systems Conference (DCAS) Pub Date : 2014-11-24 DOI: 10.1109/DCAS.2014.6965344
Pratheep Bondalapati, W. Namgoong, M. Torlak
{"title":"Modeling and compensation of antenna RF switching non-idealities in OFDM receivers","authors":"Pratheep Bondalapati, W. Namgoong, M. Torlak","doi":"10.1109/DCAS.2014.6965344","DOIUrl":"https://doi.org/10.1109/DCAS.2014.6965344","url":null,"abstract":"Antenna RF switches are radio frequency components used in spatial diversity systems in wireless communi-cations. In this paper, we investigate the transient effects of the antenna RF switching on the receiver front-end. We show experimentally that the duration of this effect can be significant compared to an OFDM (Orthogonal Frequency Division Multiplexing) guard period used in wireless systems. A simple memoryless time-varying model of the antenna is then developed. After quantifying the performance degradation in an OFDM system caused by the RF switching, a digital compensator to minimize this performance degradation is presented.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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