Effect of switchbox topologies and net ordering on 3D FPGA routing

Abstract

The growing need for smaller form factors of smartphones and other handheld devices with greater computational capabilities has resulted in the emergence of stacked silicon (3D) architectures (also referred to as 2.SD type of devices by industry). The emergence of such devices requires us to re-evaluate existing CAD approaches to placement and routing. The extension of well established place and route tools to stacked (3D) FPGAs poses a new set of challenges. This short preliminary study uses a well known academic tool, TPR (Three-dimensional place and route) to examine the impact of switchbox topologies and net ordering on routing of stacked FPGAs. The results of this study indicate that routing multi-layer nets first yield better overall routing. This study also proposes some future avenues of research that need to be explored to thoroughly understand this problem.