{"title":"A 14-b, 0.1ps resolution coarse-fine time-to-digital converter in 45 nm CMOS","authors":"Huihua Huang, C. Sechen","doi":"10.1109/DCAS.2014.6965319","DOIUrl":null,"url":null,"abstract":"A 14-b, 0.1ps resolution interpolating coarse - fine Time-to-Digital Converter (TDC) has been developed in 45nm CMOS technology. It is based on an asynchronous buffer delay line and an RC delay line. A lookup-table (LUT) based calibration scheme was developed to correct non-linearities due to PVT variations.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2014.6965319","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A 14-b, 0.1ps resolution interpolating coarse - fine Time-to-Digital Converter (TDC) has been developed in 45nm CMOS technology. It is based on an asynchronous buffer delay line and an RC delay line. A lookup-table (LUT) based calibration scheme was developed to correct non-linearities due to PVT variations.