Variation resilient high performance and low voltage single ended sense amplifier

Sense Amplifier is an essential component in an embedded memory. Multiple voltage mode sensing techniques have been developed for embedded SRAMs where differential on bitlines is sensed and amplified to read the data from SRAM bitcell. Unlike SRAMs, embedded CMOS Read Only Memories (ROMs) have unique challenges. ROM cell is typically a single NMOS transistor and hence differential voltage is not available for ROM bit sensing. For area efficiency, a large number of bitcells is stitched on the bitline. This creates an additional bottleneck for ROM sensing where sense amplifier has to sense the data correctly for the least Ion (`ON' current of a transistor) and for the maximum Ioff (`OFF' current of transistors on a bitline). Process variation, device mismatch and temperature adversely affect Ion to Ioff ratio imposing further constraint to ROM sensing. Additionally, large bitline capacitance limits the ROM performance. As ROM bitline pitch is extremely limited, sense amplifier has to fit into the restricted layout area. Low Voltage operation adds to the list of challenges. Novel Sense Amplifier techniques need to address these challenges. This paper describes sensing techniques to overcome ROM specific problems; Supplemented Inverter based Sense Amplifier (SISA) has been introduced and compared against Diode Mirrored Resistive Sense Amplifier (DMRS). SISA is implemented in 28nm Low Power process node. This sense amplifier is proven in Silicon and works across splits down up to 0.7v. 2ns access time is achieved for 1Mb instance. SISA is also proven in multiple other ultra-low power technology nodes.