{"title":"预测ADC:低功耗ADC设计的新方法","authors":"Nicholas Wood, Nan Sun","doi":"10.1109/DCAS.2014.6965323","DOIUrl":null,"url":null,"abstract":"In this paper we present a scaling friendly supplement to ADC designs which can produce increases in conversion speed and power efficiency by attempting to predict the value of the next sample. To accomplish this we use a first order difference equation to predict the values of several of the bits in the next sample. In doing so, we can save power by reducing the number of comparisons and by reducing the capacitor array switching power.","PeriodicalId":138665,"journal":{"name":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Predicting ADC: A new approach for low power ADC design\",\"authors\":\"Nicholas Wood, Nan Sun\",\"doi\":\"10.1109/DCAS.2014.6965323\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present a scaling friendly supplement to ADC designs which can produce increases in conversion speed and power efficiency by attempting to predict the value of the next sample. To accomplish this we use a first order difference equation to predict the values of several of the bits in the next sample. In doing so, we can save power by reducing the number of comparisons and by reducing the capacitor array switching power.\",\"PeriodicalId\":138665,\"journal\":{\"name\":\"2014 IEEE Dallas Circuits and Systems Conference (DCAS)\",\"volume\":\"167 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Dallas Circuits and Systems Conference (DCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCAS.2014.6965323\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Dallas Circuits and Systems Conference (DCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCAS.2014.6965323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Predicting ADC: A new approach for low power ADC design
In this paper we present a scaling friendly supplement to ADC designs which can produce increases in conversion speed and power efficiency by attempting to predict the value of the next sample. To accomplish this we use a first order difference equation to predict the values of several of the bits in the next sample. In doing so, we can save power by reducing the number of comparisons and by reducing the capacitor array switching power.
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