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2008 International Conference on Field Programmable Logic and Applications最新文献

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Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC 面向SOPC图像处理的粗粒度动态可重构协处理器
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630003
A. Lindoso, L. Entrena, J. Izquierdo, J. Liu-Jimenez
{"title":"Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC","authors":"A. Lindoso, L. Entrena, J. Izquierdo, J. Liu-Jimenez","doi":"10.1109/FPL.2008.4630003","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630003","url":null,"abstract":"In this paper a coarse-grain dynamically reconfigurable coprocessor for image processing is presented. This coprocessor is the main component of a System on a Programmable Chip (SoPC). The coprocessor can accelerate a wide range of image processing tasks and can be configured in a few clock cycles. The coprocessor performance and reconfiguration functionality has been tested with algorithms that involve several reconfiguration steps and microprocessor interaction. Experimental results demonstrate that the SoPC based on a 100 MHz soft microprocessor core can reach much better performance than a 3.2 GHz PC.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129131690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An optimization method of DMA transfer for a general purpose reconfigurable machine 一种通用可重构机器的DMA传输优化方法
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630030
Sayaka Shida, Yuichiro Shibata, K. Oguri, D. Buell
{"title":"An optimization method of DMA transfer for a general purpose reconfigurable machine","authors":"Sayaka Shida, Yuichiro Shibata, K. Oguri, D. Buell","doi":"10.1109/FPL.2008.4630030","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630030","url":null,"abstract":"DMA transfer between a CPU and an FPGA often becomes a bottleneck of current reconfigurable machines. The DMA transfer of the machines like SRC-6 supports streaming processing with on-board memory interleaving, but as a pre-processing of the interleaving, the CPU must reorder the data for applications with severe FPGA resource constraints. This paper empirically evaluates this overhead to reveal the trade-off point. The results show that a speedup is achieved by interleaved streaming DMA when 150 KB or lower data strings are transferred.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127835889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A non-volatile run-time FPGA using thermally assisted switching MRAMS 使用热辅助开关MRAMS的非易失性运行时FPGA
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629974
Yoann Guillemenet, L. Torres, G. Sassatelli, N. Bruchon, Ilham Hassoune
{"title":"A non-volatile run-time FPGA using thermally assisted switching MRAMS","authors":"Yoann Guillemenet, L. Torres, G. Sassatelli, N. Bruchon, Ilham Hassoune","doi":"10.1109/FPL.2008.4629974","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629974","url":null,"abstract":"This paper describes the integration of a thermally assisted switching magnetic random access memory (TAS-MRAM) in FPGA design. The non-volatility of the latter is achieved through the use of magnetic tunneling junctions (MTJ) in the MRAM cell. A thermally assisted switching scheme is used to write data in the MTJ device, which helps to reduce power consumption during write operation in comparison to the writing scheme in classical MTJ device. Plus, the non-volatility of such a design should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM based FPGAs. A real time reconfigurable (RTR) micro-FPGA using TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114613675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter 基于线性插入分选器的CFAR检测器的通用硬件架构
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629985
Roberto Perez-Andrade, R. Cumplido, C. F. Uribe, Fernando Martin del Campo
{"title":"A versatile hardware architecture for a CFAR detector based on a linear insertion sorter","authors":"Roberto Perez-Andrade, R. Cumplido, C. F. Uribe, Fernando Martin del Campo","doi":"10.1109/FPL.2008.4629985","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629985","url":null,"abstract":"This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detectors require sorting, a linear sorter based on a first in first out (FIFO) schema is used. The proposed architecture can be used as a specialized module or co-processor for software defined radar (SDR) applications. The results of implementing the architecture on a field programmable gate array (FPGA) are presented and discussed.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117245886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SPP1148 booth: Seamless design flow for reconfigurable systems SPP1148展位:可重构系统的无缝设计流程
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629959
Andreas Schallenberg, A. Rettberg, W. Nebel, F. Rammig
{"title":"SPP1148 booth: Seamless design flow for reconfigurable systems","authors":"Andreas Schallenberg, A. Rettberg, W. Nebel, F. Rammig","doi":"10.1109/FPL.2008.4629959","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629959","url":null,"abstract":"Today, using dynamic partial reconfiguration of FPGAs leads to a longer and less predictable design cycle. To improve this, we developed a modelling, simulation, and synthesis framework for partial reconfiguration, named OSSS+R. It reduces design time and hides some of the complexity. The tool PART-E integrates the results into the Xilinx early access partial reconfiguration (EAPR) flow. It eases floorplanning, bus macro instantiation, and bitstream generation. We show OSSS+R modelling, simulation and Part-E in a hands-on fashion. Synthesis to VHDL is demonstrated, too.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129386893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SPP1148 booth: Application-specific reconfigurable processors SPP1148展位:特定于应用程序的可重构处理器
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629958
H. Hinkelmann, P. Zipf, M. Glesner, M. Alles, Timo Vogt, N. Wehn, G. Kappen, T. Noll
{"title":"SPP1148 booth: Application-specific reconfigurable processors","authors":"H. Hinkelmann, P. Zipf, M. Glesner, M. Alles, Timo Vogt, N. Wehn, G. Kappen, T. Noll","doi":"10.1109/FPL.2008.4629958","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629958","url":null,"abstract":"Application-specific reconfigurable processor architectures provide a remarkable potential for systems which achieve concurrently high performance, area efficiency, energy efficiency, run-time adaptivity, and sufficient flexibility. Thus, they represent competitive design alternatives that provide significant improvements in some of these figures of merit in comparison to non-reconfigurable architectures. Research results of three projects on the analysis of architecture concepts, design, and evaluation of application-specific reconfigurable processors in different domains are presented.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132830394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Compiled hardware acceleration of Molecular Dynamics code 编译硬件加速的分子动力学代码
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630035
J. Villarreal, W. Najjar
{"title":"Compiled hardware acceleration of Molecular Dynamics code","authors":"J. Villarreal, W. Najjar","doi":"10.1109/FPL.2008.4630035","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630035","url":null,"abstract":"The objective of molecular dynamics (MD) simulations is to determine the shape of a molecule in a given biomolecular environment. These simulations are very demanding computationally, where simulations of a few milliseconds can take days or months depending on the number of atoms involved. Therefore, MD simulations are a prime candidate for FPGA-based code acceleration. We have investigated the possible acceleration of the commonly used MD program NAMD. This code is highly optimized for software based execution and does not benefit from an FPGA-based acceleration as written. We have therefore developed a modified version, based on the calculations NAMD performs, that streams a set of data through a highly pipelined circuit on the FPGA. We have used the ROCCC compiler toolset to generate the circuit and implemented it on the SGI Altix 4700 fitted with a RASC RC100 blade.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133426388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation 基于fpga实现的多值输入和输出函数的符号分解
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629970
S. Deniziak, M. Wisniewski
{"title":"An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation","authors":"S. Deniziak, M. Wisniewski","doi":"10.1109/FPL.2008.4629970","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629970","url":null,"abstract":"In this paper a method for symbolic decomposition of functions with multi-valued inputs and outputs is presented. Decomposition is performed simultaneously with an encoding of symbolic values. In this way an impact of input/output encoding on decomposition efficiency is taken into consideration during optimization. The input/output encoding is built in the balanced decomposition strategy based on parallel and serial functional decompositions. The experimental results show that the presented method significantly reduces the cost of a FPGA implementations for most evaluated benchmarks.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130409740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On-the-fly attestation of reconfigurable hardware 可重构硬件的动态认证
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629910
R. Chaves, G. Kuzmanov, L. Sousa
{"title":"On-the-fly attestation of reconfigurable hardware","authors":"R. Chaves, G. Kuzmanov, L. Sousa","doi":"10.1109/FPL.2008.4629910","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629910","url":null,"abstract":"This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfigurable device is described by a binary bitstream, the hash value of this bitstream can be calculated to validate the hardware structure. To optimize this attestation, the hash value computation is implemented in hardware on the FPGA itself. To guarantee the integrity of the existing computation architecture, the proposed hardware module also enforces region delimitation. With the region delimitation, only the regions intended to be reconfigured can be modified. Implementation results suggest that this bitstream attestation can be performed without imposing an extra delay to the reconfigurable process and at an area cost of less that 10% of a Virtex II Pro 30 FPGA device.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129883048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Mining Association Rules with systolic trees 利用收缩树挖掘关联规则
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629922
S. Sun, Joseph Zambreno
{"title":"Mining Association Rules with systolic trees","authors":"S. Sun, Joseph Zambreno","doi":"10.1109/FPL.2008.4629922","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629922","url":null,"abstract":"Association Rules Mining (ARM) algorithms are designed to find sets of frequently occurring items in large databases. ARM applications have found their way into a variety of fields, including medicine, biotechnology, and marketing. This class of algorithm is typically very memory intensive, leading to prohibitive runtimes on large databases. Previous attempts at acceleration using custom or reconfigurable hardware have been limited, as many of the significant ARM algorithms were designed from a software developerpsilas perspective and have features (e.g. dynamic linked lists, recursion) that do not translate well to hardware. In this paper we look at how we can accomplish the goal of association rules mining from a hardware perspective. We investigate a popular tree-based ARM algorithm (FP-growth), and make use of a systolic tree structure, which mimics the internal memory layout of the original software algorithm while achieving much higher throughput. Our experimental prototype demonstrates how we can trade memory resources on a software platform for computational resources on a reconfigurable hardware platform, in order to exploit a fine-grained parallelism that was not inherent in the original ARM algorithm.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130319455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
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