A versatile hardware architecture for a CFAR detector based on a linear insertion sorter

Abstract

This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detectors require sorting, a linear sorter based on a first in first out (FIFO) schema is used. The proposed architecture can be used as a specialized module or co-processor for software defined radar (SDR) applications. The results of implementing the architecture on a field programmable gate array (FPGA) are presented and discussed.