{"title":"An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation","authors":"S. Deniziak, M. Wisniewski","doi":"10.1109/FPL.2008.4629970","DOIUrl":null,"url":null,"abstract":"In this paper a method for symbolic decomposition of functions with multi-valued inputs and outputs is presented. Decomposition is performed simultaneously with an encoding of symbolic values. In this way an impact of input/output encoding on decomposition efficiency is taken into consideration during optimization. The input/output encoding is built in the balanced decomposition strategy based on parallel and serial functional decompositions. The experimental results show that the presented method significantly reduces the cost of a FPGA implementations for most evaluated benchmarks.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Field Programmable Logic and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPL.2008.4629970","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper a method for symbolic decomposition of functions with multi-valued inputs and outputs is presented. Decomposition is performed simultaneously with an encoding of symbolic values. In this way an impact of input/output encoding on decomposition efficiency is taken into consideration during optimization. The input/output encoding is built in the balanced decomposition strategy based on parallel and serial functional decompositions. The experimental results show that the presented method significantly reduces the cost of a FPGA implementations for most evaluated benchmarks.