Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC

Abstract

In this paper a coarse-grain dynamically reconfigurable coprocessor for image processing is presented. This coprocessor is the main component of a System on a Programmable Chip (SoPC). The coprocessor can accelerate a wide range of image processing tasks and can be configured in a few clock cycles. The coprocessor performance and reconfiguration functionality has been tested with algorithms that involve several reconfiguration steps and microprocessor interaction. Experimental results demonstrate that the SoPC based on a 100 MHz soft microprocessor core can reach much better performance than a 3.2 GHz PC.